Datasheet

Port output
enable 3
(POE3)
• Control of the high-impedance state of the MTU3 and GPT’s waveform
output pins
• 5 pins for input from signal sources: POE0, POE4, POE8, POE10,
POE11
• Initiation on detection of short-circuited outputs (detection of
simultaneous switching of large-current pins to the active level)
• Initiation by comparator-detection of analog level input to the 12-bit
A/D converter
• Initiation by oscillation-stoppage detection
• Initiation by software
• Selection of which output pins should be placed in the high-impedance
state at the time of each POE input or comparator detection
Timer
General PWM
timer (GPT)
• 16 bits x 4 channels
• Counting up or down (saw-wave), counting up and down
(triangle-wave) selectable for all channels
• Clock sources independently selectable for all channels
• 2 input/output pins per channel
• 2 output compare/input capture registers per channel
• For the 2 output compare/input capture registers of each channel, 4
registers are provided as buffer registers and are capable of operating
as comparison registers when buffering is not in use.
• In output compare operation, buffer switching can be at peaks or
troughs, enabling the generation of laterally asymmetrically PWM
waveforms.
• Registers for setting up frame intervals on each channel (with
capability for generating interrupts on overflow or underflow)
• Operation of the several counters may be synchronized
• Modes of synchronized operation (synchronized, or displaced by
desired times for phase shifting)
• Generation of dead times in PWM operation
• Through combination of three counters, generation of automatic
three-phase PWM waveforms incorporating dead times
• Starting, clearing, and stopping counters in response to external or
internal triggers
• Internal trigger sources: output of the internal comparator detection,
software, and compare-match
• The frequency-divided system clock (ICLK) can be used as a counter
clock for measuring timing of the edges of signals produced by
frequency-dividing the low-speed on-chip oscillator clock signal
dedicated to IWDT (to detect abnormal oscillation).
Compare match
timer (CMT)
• (16 bits x 2 channels) x 2 units
• Select from among four internal clock signals (PCLK/8, PCLK/32,
PCLK/128, PCLK/512)