Datasheet

Table 1.1 Specifications (1)
Item Function Specification
CPU Central
processing unit
Rx600 CPU core
• Number of fundamental instructions: 73
• Minimum instruction execution time:
10 ns (f(XIN) = 100 MHz, VCC = 2.7 V to 5.5 V)
• Multiplier: 32 bits × 32 bits → 64 bits
• Divider: 32 bits / 32 bits → 32 bits
• Barrel shifter: 32 bits
• Operating mode: Single-chip mode (address space: 4 Gbyte linear)
Memory ROM, RAM,
data flash
See Table 1.3 Products List.
Reset sources
• Hardware reset by RESET#
• Power-on reset
• Reset from two Watchdog timers
• Software reset
• Reset by voltage detection
Voltage
detection
Voltage
detection circuit
When voltage on detection When the voltage on VCC falls below the voltage
detection level (Vdet), an internal reset or internal interrupt is generated.
Watchdog timer
• 8 bits x 1 channel
• Select from among eight counter-input clock signals (PCLK/4, PCLK/64,
PCLK/128, PCLK/512, PCLK/2048, PCLK/8192, PCLK/32768,
PCLK/131072)
• Switchable between watchdog timer mode and interval timer mode
Independent
Watchdog timer
(IWDT)
• 14 bits x 1 channel
• Counter-input clock: low-speed on-chip oscillator dedicated to IWDT
Clock Clock
generation
circuits
• One circuit: Main clock oscillator
• Internal oscillator: Low-speed on-chip oscillator dedicated to IWDT
• Structure of a PLL frequency synthesizer and frequency divider for
selectable operating frequency
• Oscillation stoppage detection
• Independent frequency-division and multiplication settings for the system
clock (ICLK) and peripheral module clock (PCLK)
• The CPU and system sections such as other bus masters, MTU3, and
GPT run in synchronization with the system clock (ICLK): 8 to 100 MHz.
• Peripheral modules run in synchronization with the peripheral module
clock (PCLK): 8 to 50 MHz
Power control
• Standard operating mode
• Sleep mode
• All-module clock stop mode
• Software standby mode
• Deep software standby mode