Datasheet

R01DS0041EJ0150 Rev.1.50 Page 148 of 221
Oct 18, 2013
RX210 Group 5. Electrical Characteristics
5.3.1 Clock Timing
Note 1. When the EXTAL external clock input is used with divided by 1 (SCKCR.BCK[3:0] bits = 0000b and BCKCR.BCLKDIV bit = 0) to
output from the BCLK pin, the above should be satisfied with a duty cycle of 45 to 55%.
Note 1. When the EXTAL external clock input is used with divided by 1 (SCKCR.BCK[3:0] bits = 0000b and BCKCR.BCLKDIV bit = 0) to
output from the BCLK pin, the above should be satisfied with a duty cycle of 45 to 55%.
Note: • Set high driving ability for the output port pin to be used for the BCLK pin function.
Note 1. When the EXTAL external clock input is used with divided by 1 (SCKCR.BCK[3:0] bits = 0000b and BCKCR.BCLKDIV bit = 0) to
output from the BCLK pin, the above should be satisfied with a duty cycle of 45 to 55%.
Table 5.41 BCLK Timing (1)
Conditions: VCC = AVCC0 = 2.7 to 5.5 V, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
fBCLK = up to 25 MHz (BCLK pin output frequency = up to 12.5 MHz), T
a
= –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
BCLK pin output cycle time t
Bcyc
80 — — ns Figure 5.59
BCLK pin output high pulse width*
1
t
CH
20 — — ns
BCLK pin output low pulse width*
1
t
CL
20 — — ns
BCLK pin output rising time t
Cr
— — 15 ns
BCLK pin output falling time t
Cf
— — 15 ns
Table 5.42 BCLK Timing (2)
Conditions: VCC = AVCC0 = 1.8 to 2.7 V, VSS = AVSS0 = VREFL = VREFL0 = 0 V,
fBCLK = up to 16 MHz (BCLK pin output frequency= up to 8 MHz), T
a
= –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
BCLK pin output cycle time t
Bcyc
125 — — ns Figure 5.59
BCLK pin output high pulse width*
1
t
CH
30 — — ns
BCLK pin output low pulse width*
1
t
CL
30 — — ns
BCLK pin output rising time t
Cr
— — 25 ns
BCLK pin output falling time t
Cf
— — 25 ns
Table 5.43 BCLK Timing (3)
Conditions: VCC = AVCC0 = 1.62 to 1.8 V, VSS = AVSS0 = VREFL=VREFL0 = 0 V,
fBCLK = up to 12 MHz (BCLK pin output frequency = up to 6 MHz), T
a
= –40 to +105°C
Item Symbol Min. Typ. Max. Unit Test Conditions
BCLK pin output cycle time t
Bcyc
166.6 — — ns Figure 5.59
BCLK pin output high pulse width*
1
t
CH
42 — — ns
BCLK pin output low pulse width*
1
t
CL
42 — — ns
BCLK pin output rising time t
Cr
— — 35 ns
BCLK pin output falling time t
Cf
— — 35 ns