Datasheet

R01DS0041EJ0150 Rev.1.50 Page 168 of 221
Oct 18, 2013
RX210 Group 5. Electrical Characteristics
Figure 5.81 Example of Operation in Read Access over the External Bus (Multiplexed)
Figure 5.82 Example of Operation in Write Access over the External Bus (Multiplexed)
Address/
data bus
Data read
(RD#)
t
AD
BCLK
Address
Address latch
(ALE)
Chip select
(CS3# to CS0#)
T
W1
T
Wn
t
AD
t
AD
t
SU(DB-RD)
40 ns (min)
T
end
Address cycle
Data cycle
t
ALED
t
CSD
t
CSD
T
n1
T
h
1 cycle fixed
Address cycle wait (AWAIT)
t
S(DB-RD) 0 ns (min)
t
RSD
t
RSS
t
RSD
t
RSS
Read-access CS extension cycle
(CSROFF)
t
ALED
RD assert wait (RDON)
Normal read cycle wait (CSRWAIT)
CS assert wait (CSON)
A D
t
RDH
t
RDS
t
d(AD-ALE)
t
h(ALE-AD)
Address/
data bus
Data write
(WR#)
t
AD
BCLK
Address
Address latch
(ALE)
Chip select
(CS3# to CS0#)
T
W1
t
AD
t
AD
T
end
Address cycle
Data cycle
t
CSD
t
CSD
T
n1
T
h
1 cycle fixed
t
d(BCLK-ALE)=
t
ALED
Address cycle wait (AWAIT)
t
RSD
t
RSS
t
RSD
t
RSS
WR assert wait (WRON)
Normal write cycle wait (CSRWAIT)
A D
Write data output wait (WDON)
t
d(BCLK-ALE)=
t
ALED
A
Read-access CS extension cycle
(CSROFF)