Datasheet

R01DS0041EJ0150 Rev.1.50 Page 172 of 221
Oct 18, 2013
RX210 Group 5. Electrical Characteristics
Note 1. t
Pcyc
: PCLK cycle
Note 2. Divided by 2 can be set only in packages with 768 Kbytes/1 Mbyte of flash memory or 144/145 pins.
Item Symbol Min. Max. Unit*
1
Test Conditions
RSPI Data input setup time Master 2.7 V ≤ VCC ≤ 5.5 V t
SU
10 — ns C = 30pF
Figure 5.92 to
Figure 5.97
1.8 V ≤ VCC < 2.7 V 25 —
1.62 V ≤ VCC < 1.8 V 30 —
Slave 25 – t
Pcyc
—
Data input hold time Master PCLKB set to a
division ratio other
than divided by 2
t
H
t
Pcyc
—ns
PCLKB set to divided
by 2*
2
t
HF
0—
Slave t
H
20 + 2 × t
Pcyc
—
SSL setup time Master t
LEAD
18t
SPcyc
Slave 4 — t
Pcyc
SSL hold time Master t
LAG
18t
SPcyc
Slave 4 — t
Pcyc
Data output delay
time
Master 2.7 V ≤ VCC ≤ 5.5 V t
OD
—14ns
1.8 V ≤ VCC < 2.7 V — 20
1.62 V ≤ VCC < 1.8 V — 25
Slave 2.7 V ≤ VCC ≤ 5.5 V — 3 × t
Pcyc
+ 65
1.8 V ≤ VCC < 2.7 V — 3 × tPcyc +85
1.62 V ≤ VCC < 1.8 V — 3 × tPcyc +95
Data output hold time Master t
OH
0—ns
Slave 0 —
Successive
transmission delay
time
Master t
TD
t
SPcyc
+ 2 × t
Pcyc
8 × t
SPcyc
+ 2
× t
Pcyc
ns
Slave 4 × t
Pcyc
—
MOSI and MISO rise/
fall time
Output 2.7 V ≤ VCC ≤ 5.5 V t
Dr,
t
Df
—10ns
1.8 V ≤ VCC < 2.7 V — 15
1.62 V ≤ VCC < 1.8 V — 20
Input — 1 μs
SSL rise/fall time Output 2.7 V ≤ VCC ≤ 5.5 V t
SSLr,
t
SSLf
—10ns
1.8 V ≤ VCC < 2.7 V — 15
1.62 V ≤ VCC < 1.8 V — 20
Input — 1 μs
Slave access time 2.7 V ≤ VCC ≤ 5.5 V t
SA
—6t
Pcyc
C = 30pF
Figure 5.96 and
Figure 5.97
1.8 V ≤ VCC < 2.7 V — 7
1.62 V ≤ VCC < 1.8 V — 7
Slave output release time 2.7 V ≤ VCC ≤ 5.5 V t
REL
—5t
Pcyc
1.8 V ≤ VCC < 2.7 V — 6
1.62 V ≤ VCC < 1.8 V — 6