User Manual

RF Technology R220 Page 13
5 CIRCUIT DESCRIPTION
5.2 IF Section
A two pole 45 MHz crystal filter XF1 is used between the first and second IF
amplifiers. The second IF amplifier Q4 provides additional gain of 6-10dB. A two
pole crystal filter is used between Q4 and the 2nd oscillator mixer. These two crystal
filters provide some adjacent channel rejection and all of the second IF image
frequency rejection.
U1 is a monolithic oscillator and mixer IC. It converts the 45 MHz IF signal down to
455 KHz. The second oscillator frequency or 45.455 MHz is controlled by crystal
Y1. The 455 KHz output of the second mixer is fed through a ceramic filter CF1 to
the second IF amplifier transistor Q27. Q27 provides an additional 15 dB gain ahead
of the limiter and discriminator IC U3.
The limiter/discriminator IC U3 further amplifies the signal and passes it through
CF2. CF2 does not contribute to the adjacent channel rejection but is used to reduce
the wide band noise input to the limiter section of U3.
The limiter section of U3 drives the quadrature detector discriminator. C31 and IF
tuned circuit L10 comprise the discriminator phase shift network.
U3 also has a received signal strength indicator output (RSSI). The RSSI voltage
connects to the test socket for alignment use. The RSSI voltage is also used by the
microprocessor for the adaptive noise squelch, carrier squelch and low signal alarm
functions.
Dual op-amp U2 is used to amplify and buffer the discriminator audio and RSSI
outputs.
5.3 VCO Section
The Voltage Controlled Oscillator uses a junction FET Q6 which oscillates at the
required mixer injection frequency. Varactor diode D4 is used by the PLL circuit to
keep the oscillator on the desired frequency. Transistor Q7 is used as a filter to
reduce the noise on the oscillator supply voltage.
5.4 PLL Section
The synthesizer frequency reference is supplied by a temperature compensated
crystal oscillator (XO1). The frequency stability of the oscillator is better than 1
ppm.
The 12 MHz output of Q25 or XO1 is amplified by Q8 to drive the reference input
of the PLL synthesizer IC U4. This IC is a single chip synthesizer which includes a
1.1 GHz pre-scaler, programmable divider, reference divider and phase/frequency
detector. The frequency data is entered a serial data link from the microprocessor.
The phase detector output signals of U4 are used to control two switched current
sources. The output of the positive and negative sources' Q10 and Q16, produce the
tuning voltage which is smoothed by the loop filter components to bias the VCO
varactor diode D4.