Operating instructions

Page 8 RF Technology R50
FPSW1, FPSW2 and FPSW3 are three pins that have been reserved for future use as
switch inputs.
LOOP/VOLTS_SEL is a CPU output that when high applies 12V of dc feed to the
audio output.
LINE_LEVEL_U/D and LINE_LEVEL_INC are CPU outputs which are reserved for
controlling a digital potentiometer in future.
COS_VOLTS_ON/OFF is a CPU output that when high applies 12VDC feed to
COS+ terminal, so that the COS can be selected as +12VDC source or a free
switch.
COS_POLARITY is CPU output that when low turns
Opto-coupled
transistor switch
U601on. It is controlled by the noise squelch detect, carrier squelch, or
external squelch signal
SQ is a CPU output that when low, enables the 600 ohm line output, and the direct
audio output. It is controlled by the noise squelch detect, carrier squelch, or
external squelch signal
N_BLK_EN is a CPU output that when low turns noise blanker option off.
CTCSS_SEL is a serial bus select pin. It is used to select the FX805 chip(U500),
which is used to decode CTCSS tones. (see 5.5)
PLL_SEL is a serial bus select pin. It is used to select the PLL chip in the PLL circuit
(U302). (See 5.6)
RCV_ADSEL is a serial bus select pin. It selects the quad Digital to Analogue
converter (DAC) that sets the levels for the 12MHz reference oscillator bias
voltage, 21.855MHz oscillator bias voltage, noise squelch
comparator bias
voltage and the LCD bias circuit. (see 5.4)
CH_EN is a serial bus select. It is brought out to the rear panel and is used to
interface to the channel encoder on the rear daughter-board. (See 5.1)
FLAT and DE_EMPHA are outputs which are the logical inverse of one another.
When the FLAT pin is low, the audio output is flat response, when
DE_EMPHA pin low, audio is 750uSec de-emphasized.
Fo_PLL is derived from the
the Fo output
of the PLL chip. It is Fo after being
divided by 100. They should be 312.5Hz square waves, except for brief
periods when frequencies are being changed. (See 5.6)
MON_SW is a digital
input which represents the state of the front panel MON.SQ
switch.
LCD_DB7 is a signal that has been reserved for interfacing to an LCD display.
ECLK is a pin that at start-up only, should have the CPU system clock of 7.3728MHz
on it.
SQ_LED, ALARM_LED, are CPU outputs that drive (when low) the SQ LED, and
the ALARM LED.
T/R_RELAY_H is a spare pin which is not used in the R50 receiver.
SCLK, and MOSI are used as the core of a serial bus. SCLK is a clock pin, and
MOSI is a bi-directional data pin.
DBGTX_TTL, DBGRX_TTL are RS232 transmit and receive (TTL) data pins which
are connected to the debug port after conversion to/from RS232 compatible
voltage levels by U202 and U201.