Operating instructions

RF Technology R50 Page 9
TXD_TTL, RXD_TTL, RTS_TTL, CTS_TTL, DTR_TTL, DSR_TTL, are RS232
data pins which are connected to the main front panel serial port, after
conversion to/from RS232 compatible voltage levels by U202 and U201.
N_DET is used to sense the noise squelch output of the receiver section. (see)
SUBTONE_IRQ is connected to the interrupt pin of the FX805 (U500). When
CTCSS tones change state, ie a new tone is detected, or an existing tone stops
being received, or 8 bits of NRZ data (when decoding DCS codes) are
received, this signal is asserted to force the CPU to read data from U500.
INT is a dedicated CPU interrupt input pin. It is used to detect the state of the external
squelch signal.
BKGD is a bi-directional I/O pin used to communicate with the core of the CPU. It is
connected to the debug port and is utilised by specialised hardware to control
the CPU externally, even without any firmware being present in the Flash.
The RESET pin is both a low active input and a low active output to the CPU. If
generated externally to the CPU, it forces the CPU into reset, and if the CPU
executes a RESET instruction
this pin will be driven low by the CPU.
Whenever there is insufficient volts (< 4.65V) on pin 2 of the MC33064D (U203), it
will keep its RES output low. After the voltage has met the right level it will
assert its output low for another 200 milliseconds. Thus the CPU will be held
in reset until VCC is at the correct level. Thus the PWR_OK LED will only
light when VCC is within specification, and RESET has been released.
S200 is a momentary push-button switch that, when pressed, will cause the CPU to be
reset.
MON_SQ is a CPU output which is used to enable (when low), or disable (when high)
the audio at the monitor speaker.
LCD_RS, LCD_R/W, and LCD_E are reserved for interfacing to
an LCD display
module. Note that this feature has not been implemented.
U205 is used to select whether the Flash or RAM is to be read or written.
U207 is a single supply, 5V, TSOP40 Flash chip of size 8, 16, or 32 Megabits, and is
used to store the firmware.
U208 is a 1, or 4
, Megabit Static RAM in an SOP-32 package, and is used for both
code and data. The code in the RAM is copied from the Flash, at start-up.
5.3 RF Section (Sheet 3)
Sheet 3 is a schematic of the RF section, which itself refers to two other
subsheets.
U301 is a quad Digital to Analogue converter (DAC). OUTA (pin2) is used to adjust
the 3rd local oscillator frequency. OUTB (pin1) is used to adjust the frequency
of the 12MHz reference. OUTC(pin16) is used to set the noise squelch
comparator offset voltage. OUTD (pin15) is reserved for future use.
Communication between U301 and the
MicroController, U204, is via the serial
bus.
U302 is a dual channel PLL chip, X301 is the reference for both PLL channels. PLL
channel 1 is for the 1st VCO, and channel 2 is for the 2nd VCO. C315, C317,
C327, R316 and R317 are components of the loop filter for the 1st VCO,
C316, C328, C329, R330 and R331 are for the loop filter of the 2nd VCO.