Data Sheet

R8002 Datasheet
-9 -
Table 3: Possible UART Settings
Parameter
Possible Values
Baudrate
Minimum 1200 baud (≤2%Error)
Standard
115200bps(≤1%Error)
Maximum
921600bps(≤1%Error)
Flow control
Supports Automatic Flow Control (CTS and
RTS lines)
Parity
None, Odd or Even
Number of stop bits
1 /1.5/2
Bits per channel
5/6/7/8
When connecting the module to a host, please make sure to follow .
Module
Host
TX RX
RX
TX
GND
GND
RTS
RTS
CTS
CTS
Figure 4: UART Connection
4.3.2 I2C Interface
I2C is a two-wire, bi-directional serial bus that provides a simple and efficient method of data exchange between
devices. The I2C standard is a true multi-master bus including collision detection and arbitration that prevents data
corruption if two or more masters attempt to control the bus simultaneously.
FSC-BT986 has I2C master which supports 100Kbps and 400Kbps.
Data is transferred between a Master and a Slave synchronously to SCL on the SDA line on a byte-by-byte basis. Each
data byte is 8-bit long. There is one SCL clock pulse for each data bit with the MSB being transmitted first. An
acknowledge bit follows each transferred byte. Each bit is sampled during the high period of SCL; therefore, the SDA
line may be changed only during the low period of SCL and must be held stable during the high period of SCL. A
transition on the SDA line while SCL is high is interpreted as a command (START or STOP). Please refer to the following
figure for more details about I2C Bus Timing.
Figure 5: I2C Bus Timing
Shenzhen Feasycom Technology Co.,Ltd