Data Sheet

Copyright © Bridgetek Pte Ltd 14
BT81X (815/6) Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000220 Clearance No.: BRT#126
Figure 4-3 Quad SPI Interface connection
4.1.2 Serial Data Protocol
The BT815/6 appears to the host MPU/MCU as a memory-mapped SPI device. The host communicates
with the BT815/6 using reads and writes to a large (4 megabyte) address space. Within this address
space are dedicated areas for graphics, audio and touch control. Refer to section 5 for the detailed
memory map.
The host reads and writes the BT815/6 address space using SPI transactions. These transactions are
memory read, memory write and command write. Serial data is sent by the most significant bit first.
Each transaction starts with CS_N goes low, and ends when CS_N goes high. There’s no limit on data
length within one transaction, as long as the memory address is continuous.
4.1.3 Host Memory Read
For SPI memory read transactions, the host sends two zero bits, followed by the 22-bit address. This is
followed by a dummy byte. After the dummy byte, the BT815/6 responds to each host byte with read
data bytes.
Byte n
Table 4-2 Host Memory Read Transaction
7
6
5
4
3
2
1
0
0
0
Address [21:16]
Address [15:8]
Address [7:0]
Dummy byte
Byte 0
GND
GND
SCLK
MISO
IO2
SS#
PD#
INT#
SCK
MISO
IO2
CS_N
PD_N
INT_N
BT815/6
1.8-3.3V
VCCIO1
3.3V
VCC
4.7k
MPU/MCU
MOSI
IO3
MOSI
IO3
Read Data
Write
Address