Data Sheet

Copyright © Bridgetek Pte Ltd 18
BT81X (815/6) Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000220 Clearance No.: BRT#126
1st Byte
2nd byte
3rd byte
Command
Description
08h
DISP
09h
DE
0Ah
VSYNC / HSYNC
0Bh
PCLK
0Ch
BACKLIGHT
0Dh
R[7:0], G[7:0], B[7:0]
0Eh
AUDIO_L
0Fh
INT_N
10h
CTP_RST_N
11h
CTP_SCL
12h
CTP_SDA
13h
SPI MISO/MOSI/IO2/IO3
14h
SPIM_SCLK
15h
SPIM_SS_N
16h
SPIM_MISO
17h
SPIM_MOSI
18h
SPIM_IO2
19h
SPIM_IO3
Others
Reserved
Note: GPIO0 shares the same pin as SPI
IO2 and GPIO1 with SPI IO3. When SPI is
set in Quad mode, IO2 and IO3 will inherit
the drive strength set in GROUP 13h;
otherwise GPIO0 and GPIO1 will inherit the
drive strength from GROUP 00h and 01h
respectively.
01110001b
xx
00000000b
71h
PIN_PD_STA
TE
During power down, all output and in/out
pins will not be driven. Please refer to Table
4-21 for their default power down state.
These settings will only be effective during
power down and will not affect normal
operations. Also note that these
configuration bits are sticky and, unlike
other configuration bits, will not reset to
default values upon exiting power down.
Only POR will reset them.