Data Sheet

Copyright © Bridgetek Pte Ltd 27
BT81X (815/6) Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000220 Clearance No.: BRT#126
REG_PCLK is the PCLK divisor. The default value is 0, which means the PCLK output is disabled. When
REG_PCLK is none 0 (1-1023), the PCLK frequency can be calculated as:
PCLK frequency = System Clock frequency / REG_PCLK
The BT815/6 system clock frequency is programmable. Some of the possible PCLK frequencies that
BT815/6 supports are listed in Table 4-11.
REG_PCLK
System Clock Frequency (MHz)
72
60(default)
48
36
24
2
36
30
24
18
12
3
24
20
16
12
8.0
4
18
15
12
9.0
6.0
5
14.5
12
9.6
7.2
4.8
6
12
10
8.0
6.0
4.0
7
10.3
8.6
6.9
5.1
3.4
8
9
7.5
6.0
4.5
3.0
9
8
6.7
5.3
4.0
2.7
10
7.2
6.0
4.8
3.6
2.4
Table 4-11 RGB PCLK Frequency
REG_PCLK_POL defines the clock polarity, with 0 for positive active clock edge, and 1 for negative clock
edge.
REG_CSPREAD controls the transition of RGB signals with respect to the PCLK active clock edge. When
REG_CSPREAD=0, R[7:0], G[7:0] and B[7:0] signals change following the active edge of PCLK. When
REG_CSPREAD=1, R[7:0] changes a PCLK clock early and B[7:0] a PCLK clock later, which helps reduce
the switching noise.
REG_DITHER enables colour dither. This option improves the half-tone appearance on displays.
Internally, the graphics engine computes the colour values at an 8 bit precision; however, the LCD colour
at a lower precision is sufficient.
REG_OUTBITS gives the bit width of each colour channel; the default is 8/8/8 bits for each R/G/B colour.
A lower value means fewer bits are output for each channel allowing dithering on lower precision LCD
displays.
REG_SWIZZLE controls the arrangement of the output colour pins, to help the PCB route different LCD
panel arrangements. Bit 0 of the register causes the order of bits in each colour channel to be reversed.
Bits 1-3 control the RGB order. Setting Bit 1 causes R and B channels to be swapped. Setting Bit 3 allows
rotation to be enabled. If Bit 3 is set, then (R, G, B) is rotated right if bit 2 is one, or left if bit 2 is zero.
REG_SWIZZLE
RGB PINS
b3
b2
b1
b0
R7, R6,
R5, R4,
R3, R2,
R1, R0
G7, G6,
G5, G4,
G3, G2,
G1, G0
B7, B6,
B5, B4,
B3, B2,
B1, B0
0
X
0
0
R[7:0]
G[7:0]
B[7:0]
0
X
0
1
R[0:7]
G[0:7]
B[0:7]
0
X
1
0
B[7:0]
G[7:0]
R[7:0]
0
X
1
1
B[0:7]
G[0:7]
R[0:7]
1
0
0
0
B[7:0]
R[7:0]
G[7:0]