Data Sheet

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BT81X (815/6) Advanced Embedded Video Engine Datasheet

Version 1.0

Document No.: BRT_000220 Clearance No.: BRT#126

4 Functional Description

The BT815/6 is a single chip, embedded video controller with the following functional blocks:

 Quad SPI Host Interface

 Quad SPI Flash Interface

 System Clock

 Graphics Engine

 Parallel RGB video interface

 Audio Engine

 Touch-screen support and interface (Resistive = BT816 / Capacitive – BT815)

 Power Management

The functions for each block are briefly described in the following subsections.

4.1 Quad SPI Host Interface

The BT815/6 uses a quad serial peripheral interface (QSPI) to communicate with host microcontrollers

and microprocessors.

4.1.1 QSPI Interface

The QSPI slave interface operates up to 30MHz. Only SPI mode 0 is supported. Refer to section 6.4.2 for

detailed timing specification. The QSPI can be configured as a SPI slave in SINGLE, DUAL or QUAD

channel modes.

By default the SPI slave operates in the SINGLE channel mode with MOSI as input from the master and

MISO as output to the master. DUAL and QUAD channel modes can be configured through the SPI slave

itself. To change the channel modes, write to register REG_SPI_WIDTH. The table below depicts the

setting.

REG_SPI_WIDTH[1:0]

Channel Mode

Data pins

Max bus speed

SINGLE – default mode

MISO, MOSI

30 MHz

DUAL

MOSI, MISO

30 MHz

QUAD

MOSI, MISO, IO2, IO3

30 MHz

Reserved

Table 4-1 QSPI Channel Selection

With DUAL/QUAD channel modes, the SPI data ports are now unidirectional. In these modes, each SPI

transaction (signified by CS_N going active low) will begin with the data ports set as inputs.

Hence, for writing to the BT815/6, the protocol will operate as in FT800, with “WR-Command/Addr2,

Addr1, Addr0, DataX, DataY, DataZ …” The write operation is considered complete when CS_N goes

inactive high.

For reading from the BT815/6, the protocol will still operate as in FT800, with “RD-Command/Addr2,

Addr1, Addr0, Dummy-Byte, DataX, DataY, DataZ”. However as the data ports are now unidirectional, a

change of port direction will occur before DataX is clocked out of the BT815/6. Therefore it is important

that the firmware controlling the SPI master changes the SPI master data port direction to “input” after

transmitting Addr0. The BT815/6 will not change the port direction till it starts to clock out DataX. Hence,

the Dummy-Byte cycles will be used as a change-over period when neither the SPI master nor slave will

be driving the bus; the data paths thus must have pull-ups/pull-downs. The SPI slave from the BT815/6

will reset all its data ports’ direction to input once CS_N goes inactive high (i.e. at the end of the current

SPI master transaction).

The diagram depicts the behaviour of both the SPI master and slave in the master read case.