Data Sheet

Copyright © Bridgetek Pte Ltd 15
BT81X (815/6) Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000220 Clearance No.: BRT#126
4.1.4 Host Memory Write
For SPI memory write transactions, the host sends a ‘1’ bit and ‘0’ bit, followed by the 22-bit address.
This is followed by the write data.
Byte n
Table 4-3 Host Memory Write Transaction
4.1.5 Host Command
When sending a command, the host transmits a 3 byte command. Table 4-5 Host Command List Error!
Reference source not found. lists all the host command functions.
For SPI command transactions, the host sends a ‘0’ bit and ‘1’ bit, followed by the 6-bit command code.
The 2
nd
byte can be either 00h, or the parameter of that command. The 3
rd
byte is fixed at 00h.
All SPI commands except the system reset can only be executed when the SPI is in the Single channel
mode. They will be ignored when the SPI is in either Dual or Quad channel mode.
Some commands are used to configure the device and these configurations will be reset upon receiving
the SPI PWRDOWN command, except those that configure the pin state during power down. These
commands will be sticky unless reconfigured or power-on-reset (POR) occurs.
1
st
Byte
2
nd
Byte
3
rd
Byte
Table 4-4 Host Command Transaction
1st Byte
2nd byte
3rd byte
Command
Description
Power Modes
00000000b
00000000b
00000000b
00h
ACTIVE
Switch from Standby/Sleep/PWRDOWN
modes to active mode. Dummy memory
read from address 0(read twice) generates
ACTIVE command.
01000001b
00000000b
00000000b
41h
STANDBY
Put BT815/6 core to standby mode. Clock
gate off, PLL and Oscillator remain on
(default). ACTIVE command to wake up.
7
6
5
4
3
2
1
0
1
0
Address [21:16]
Address [15:8]
Address [7:0]
Byte 0
7
6
5
4
3
2
1
0
0
1
Command [5:0]
Parameter for the command
0
0
0
0
0
0
0
0
Write Data
Write
Address