Data Sheet

Copyright © Bridgetek Pte Ltd 28
BT81X (815/6) Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000220 Clearance No.: BRT#126
1
0
0
1
B[0:7]
R[0:7]
G[0:7]
1
0
1
0
G[7:0]
R[7:0]
B[7:0]
1
0
1
1
G[0:7]
R[0:7]
B[0:7]
1
1
0
0
G[7:0]
B[7:0]
R[7:0]
1
1
0
1
G[0:7]
B[0:7]
R[0:7]
1
1
1
0
R[7:0]
B[7:0]
G[7:0]
1
1
1
1
R[0:7]
B[0:7]
G[0:7]
Table 4-12 REG_SWIZZLE RGB Pins Mapping
REG_HCYCLE, REG_HSIZE, REG_HOFFSET, REG_HSYNC0 and REG_HSYNC1 define the LCD horizontal
timings. Each register has 12 bits to allow programmable range of 0-4095 PCLK cycles. REG_VCYCLE,
REG_VSIZE, REG_VOFFSET, REG_VSYNC0 and REG_VSYNC1 define the LCD vertical timings. Each
register has 12 bits to allow a programmable range of 0-4095 lines.
Register
Display
Parameter
Description
Horizontal
REG_HCYCLE
T
H
Total length of line (visible and non-visible) (in PCLKs)
REG_HSIZE
T
HD
Length of visible part of line (in PCLKs)
REG_HOFFSET
T
HF
+ T
HP
+ T
HB
Length of non-visible part of line. Must be < T
H
- T
HD
(in PCLK cycles)
REG_HSYNC0
T
HF
Horizontal Front Porch (in PCLK cycles)
REG_HSYNC1
T
HF
+ T
HP
Horizontal Front Porch plus Hsync Pulse width (in PCLK
cycles)
Vertical
REG_VCYCLE
T
V
Total number of lines (visible and non-visible) (in lines)
REG_VSIZE
T
VD
Number of visible lines (in lines)
REG_VOFFSET
T
VF
+ T
VP
+ T
VB
Number of non-visible lines. Must be < T
V
- T
VD
(in lines)
REG_VSYNC0
T
VF
Vertical Front Porch (in lines)
REG_VSYNC1
T
VF
+ T
VP
Vertical Front Porch plus Vsync Pulse width (in lines)
Table 4-13 Registers for RGB Horizontal and Vertical Timings