Data Sheet

Copyright © Bridgetek Pte Ltd 42
BT81X (815/6) Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000220 Clearance No.: BRT#126
5 Memory Map
All memory and registers in the BT815/6 core are memory mapped in 22-bit address space with a 2-bit
SPI command prefix. Prefix 0'b00 for read and 0'b10 for write to the address space, 0'b01 is reserved for
Host Commands and 0'b11 undefined. The following are the memory space definition.
Start
Address
End
Address
Size
NAME
Description
00 0000h
0F FFFFh
1024 kB
RAM_G
General purpose graphics RAM
20 0000h
2F FFFFh
1024 kB
ROM
ROM codes, font table and bitmap
30 0000h
30 1FFFh
8 kB
RAM_DL
Display List RAM
30 2000h
30 2FFFh
4 kB
RAM_REG
Registers
30 8000h
30 8FFFh
4 kB
RAM_CMD
Command buffer
80 0000h
107F FFFFh
256 MB
FLASH
External NOR flash memory. Maximum
256MB. The address is used by internal
command only.
Table 5-1 BT815/6 Memory Map
Note 1: The addresses beyond this table are reserved and shall not be read or written unless otherwise
specified.
5.1 Registers
Table 5-2 shows the complete list of the BT815/6 registers. Refer to BT81X_Series_Programming_Guide,
Chapter 3 for details of the register function.
Address
(hex)
Register Name
Bit
s
r/
w
Reset
value
Description
302000h
REG_ID
8
r/o
7Ch
Identification register, always reads as
7Ch
302004h
REG_FRAMES
32
r/o
0
Frame counter, since reset
302008h
REG_CLOCK
32
r/o
0
Clock cycles, since reset
30200Ch
REG_FREQUENCY
28
r/w
60000000
Main clock frequency (Hz)
302010h
REG_RENDERMODE
1
r/w
0
Rendering mode: 0 = normal, 1 = single-
line
302014h
REG_SNAPY
11
r/w
0
Scanline select for RENDERMODE 1
302018h
REG_SNAPSHOT
1
r/w
-
Trigger for RENDERMODE 1
30201Ch
REG_SNAPFORMAT
6
r/w
20h
Pixel format for scanline readout
302020h
REG_CPURESET
3
r/w
2
Graphics, audio and touch engines reset
control. Bit2: audio, bit1: touch, bit0:
graphics