Data Sheet

Copyright © Bridgetek Pte Ltd 43
BT81X (815/6) Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000220 Clearance No.: BRT#126
Address
(hex)
Register Name
Bit
s
r/
w
Reset
value
Description
302024h
REG_TAP_CRC
32
r/o
-
Live video tap crc. Frame CRC is
computed every DL SWAP.
302028h
REG_TAP_MASK
32
r/w
FFFFFFFFh
Live video tap mask
30202Ch
REG_HCYCLE
12
r/w
224h
Horizontal total cycle count
302030h
REG_HOFFSET
12
r/w
02Bh
Horizontal display start offset
302034h
REG_HSIZE
12
r/w
1E0h
Horizontal display pixel count
302038h
REG_HSYNC0
12
r/w
000h
Horizontal sync fall offset
30203Ch
REG_HSYNC1
12
r/w
029h
Horizontal sync rise offset
302040h
REG_VCYCLE
12
r/w
124h
Vertical total cycle count
302044h
REG_VOFFSET
12
r/w
00Ch
Vertical display start offset
302048h
REG_VSIZE
12
r/w
110h
Vertical display line count
30204Ch
REG_VSYNC0
10
r/w
000h
Vertical sync fall offset
302050h
REG_VSYNC1
10
r/w
00Ah
Vertical sync rise offset
302054h
REG_DLSWAP
2
r/w
0
Display list swap control
302058h
REG_ROTATE
3
r/w
0
Screen rotation control. Allow
normal/mirrored/inverted for landscape
or portrait orientation.
30205Ch
REG_OUTBITS
9
r/w
0
Output bit resolution, 3 register bits each
for R/G/B. 0 indicates 8 bits, 1-7
indicates 1-7 bits respectively.
302060h
REG_DITHER
1
r/w
1
Output dither enable
302064h
REG_SWIZZLE
4
r/w
0
Output RGB signal swizzle
302068h
REG_CSPREAD
1
r/w
1
Output clock spreading enable
30206Ch
REG_PCLK_POL
1
r/w
0
PCLK polarity:
0 = output on PCLK rising edge,
1 = output on PCLK falling edge
302070h
REG_PCLK
8
r/w
0
PCLK frequency divider, 0 = disable
302074h
REG_TAG_X
11
r/w
0
Tag query X coordinate
302078h
REG_TAG_Y
11
r/w
0
Tag query Y coordinate
30207Ch
REG_TAG
8
r/o
0
Tag query result
302080h
REG_VOL_PB
8
r/w
FFh
Volume for playback
302084h
REG_VOL_SOUND
8
r/w
FFh
Volume for synthesizer sound
302088h
REG_SOUND
16
r/w
0
Sound effect select