Data Sheet

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BT81X (815/6) Advanced Embedded Video Engine Datasheet
Version 1.0
Document No.: BRT_000220 Clearance No.: BRT#126
6.4.3 RGB Interface Timing
Parameter
Description
Value
Units
Min
Typ
Max
Tpclk
Pixel Clock period
13.9
27.8
ns
Tpclkdc
Pixel Clock duty cycle
40
50
60
%
Td
Output delay relative to PCLK rising
edge (REG_PCLK_POL=0) or falling
edge (REG_PCLK_POL=1). Applied for
all the RGB output pins.
4
ns
Th
Output hold time relative to PCLK
rising edge (REG_PCLK_POL=0) or
falling edge (REG_PCLK_POL=1).
Applied for all the RGB output pins.
0.5
ns
Table 6-10 RGB Interface Timing Characteristics
Figure 6-2 RGB Interface Timing