User Manual

User's Guide HDSPe AES © RME
37
24. Word Clock
24.1 Word Clock Input and Output
SteadyClock guarantees an excellent performance in all clock modes. Based on the highly effi-
cient jitter suppression, the HDSPe AES refreshes and cleans up any clock signal, and provides
it as reference clock at the BNC output (see chapter 30.6).
Input
The HDSPe AES's word clock input is active when Pref. Sync Ref in the Settings dialog has
been switched to Word Clock, the clock mode AutoSync has been activated, and a valid word
clock signal is present. The signal at the BNC input can be Single, Double or Quad Speed, the
HDSPe AES automatically adapts to it. As soon as a valid signal is detected, the Settings dialog
shows either Lock or Sync (see chapter 30.2).
Thanks to RME's Signal Adaptation Circuit, the word clock input still works correctly even with
heavily mis-shaped, dc-prone, too small or overshoot-prone signals. Thanks to automatic signal
centering, 300 mV (0.3V) input level is sufficient in principle. An additional hysteresis reduces
sensitivity to 1.0 V, so that over- and undershoots and high frequency disturbances don't cause
a wrong trigger.
The word clock input is shipped as high impedance type (not terminated). An internal jumper
besides the BNC socket allows to activate proper termination (75 Ohm).
Output
The word clock output of the HDSPe AES is constantly active, providing the current sample
frequency as word clock signal. As a result, in Master mode the provided word clock is defined
by the currently used software or the Pitch dialog. In Slave mode the provided frequency is
identical to the one present at the currently chosen clock input. When the current clock signal
fails, the HDSPe AES switches to Master mode and adjusts itself to the next, best matching
frequency (44.1 kHz, 48 kHz etc.).
Selecting the options Double Wire or Quad Wire in the Settings dialog the output frequency is
changed to always be the same as the sample rate on the AES outputs. At 192 kHz operation
with activated Double Wire operation the AES will generate a word clock signal of 96 kHz.
The received word clock signal can be distributed to other devices by using the word clock out-
put. With this the usual T-adapter can be avoided, and the HDSPe AES operates as Signal
Refresher. This kind of operation is highly recommended, because
• input and output are phase-locked and in phase (0°) to each other
• SteadyClock removes nearly all jitter from the input signal
• the exceptional input (1 Vpp sensitivity instead of the usual 2.5 Vpp, dc cut, Signal Adapta-
tion Circuit) plus SteadyClock guarantee a secure function even with highly critical word
clock signals
Thanks to a low impedance, but short circuit proof output, the HDSPe AES delivers 4 Vpp to 75
Ohms. For wrong termination with 2 x 75 Ohms (37.5 Ohms), there are still 3.3 Vpp fed into the
network.