User Manual

64
User's Guide HDSPe AES © RME
29. Technical Specifications
29.1 Inputs
AES/EBU
8 x, transformer balanced, ground-free, according to AES3-1992
High-sensitivity input stage (< 0.3 Vpp)
SPDIF compatible (IEC 60958)
Accepts Consumer and Professional format, copy protection will be ignored
Single Wire: 8 x 2 channels 24 bit, up to 192 kHz
Double Wire: 8 x 2 channels 24 bit 96 kHz, equalling 8 channels 192 kHz
Quad Wire: 8 x 2 channels 24 bit 48 kHz, equalling 4 channels 192 kHz
Lock range: 28 kHz - 204 kHz
Jitter when synced to input signal: < 1 ns
Jitter suppression: > 30 dB (2.4 kHz)
Word Clock
BNC, not terminated (10 kOhm)
Internal jumper for 75 Ohm termination
Automatic Double/Quad Speed detection and conversion to Single Speed
SteadyClock guarantees super low jitter synchronization even in varispeed operation
Not effected by DC-offsets within the network
Signal Adaptation Circuit: signal refresh through auto-center and hysteresis
Overvoltage protection
Level range: 1.0 Vss – 5.6 Vpp
Lock range: 28 kHz – 204 kHz
Jitter when synced to input signal: < 1 ns
Jitter suppression: > 30 dB (2.4 kHz)
29.2 Outputs
AES/EBU
8 x, transformer balanced, ground-free, according to AES3-1992
Output voltage Professional 4.5 Vpp, Consumer 2.1 Vpp
Format Professional according to AES3-1992 Amendment 4
Format Consumer (SPDIF) according to IEC 60958
Single Wire: 8 x 2 channels 24 bit, up to 192 kHz
Double Wire: 8 x 2 channels 24 bit 96 kHz, equalling 8 channels 192 kHz
Quad Wire: 8 x 2 channels 24 bit 48 kHz, equalling 4 channels 192 kHz
Word Clock
1 x BNC
Max. output voltage: 5 Vpp
Output voltage @ 75 Ohm termination: 4.0 Vpp
Output impedance: 10 Ohm
Frequency range: 28 kHz – 204 kHz