User Manual

User's Guide HDSPe AES © RME

30.2 Lock and SyncCheck

Digital signals consist of a carrier and the data. If a digital signal is applied to an input, the re-

ceiver has to synchronize to the carrier clock in order to read the data correctly. To achieve this,

the receiver uses a PLL (Phase Locked Loop). As soon as the receiver meets the exact fre-

quency of the incoming signal, it is locked. This Lock state remains even with small changes of

the frequency, because the PLL tracks the receiver's frequency.

If a AES/EBU signal is applied to the HDSPe AES, the unit indicates LOCK, i. e. a valid input

signal. This information is presented in the HDSPe AES Settings dialog. In the status display

SyncCheck, the state of all clocks is decoded and shown as simple text (No Lock, Lock, Sync).

Unfortunately, LOCK does not necessarily mean that the received signal is correct with respect

to the clock which processes the read out of the embedded data. Example: The HDSPe AES is

set to 44.1 kHz internally (clock mode Master), and a mixing desk with AES output is connected

to the card's AES1 input. The status display will show LOCK immediately, but usually the mixing

desk's sample rate is generated internally (it is Master too), and thus slightly higher or lower

than the HDSPe AES internal sample rate. Result: When reading out the data, there will fre-

quently be read errors that cause clicks and drop outs.

Also when using multiple clock signals, a simple LOCK is not sufficient. The above described

problem can be solved elegantly by setting the HDSPe AES from Master to AutoSync (its inter-

nal clock will then be the clock delivered by the mixing desk). But in case the card is clocked to

word clock, this signal can also be un-synchronous, and there will again be a slight difference in

the sample rate, and therefore clicks and drop outs.

In order to display those problems, the HDSPe AES includes SyncCheck. It checks all clocks

used for synchronicity. If they are not synchronous to each other, the status display will show

LOCK. If they are synchronous to each other (i. e. absolutely identical) the status display will

change to SYNC. In the example above it would have been obvious immediately that the entry

LOCK is shown in SyncCheck instead of SYNC, right after connecting the mixing desk. With

external synchronisation via word clock, both entries Word Clock and AESx must display

SYNC.

In practice, SyncCheck allows for a quick overview of the correct configuration of all digital de-

vices. So one of the most difficult and error-prone topics of the digital studio world finally be-

comes easy to handle.

A special problem occurs with devices offering several AES or SPDIF inputs. While with ADAT

and TDIF all eight channels share the same clock base, with AES there are several completely

independent receivers with their own PLLs and data buffers. Therefore there can be a random

error of ± 1 sample difference between the stereo pairs. The HDSPe AES exclusive SyncA-

lign

technology avoids this effect and guarantees sample synchronicity among all four stereo

channels.