User Manual

User's Guide Fireface UC © RME
79
DA, Line Out 1-6, rear
Resolution: 24 bit
Dynamic range (DR): 110 dB, 113 dBA @ 44.1 kHz (unmuted)
Frequency response @ 44.1 kHz, -0.1 dB: 1 Hz – 20.4 kHz
Frequency response @ 96 kHz, -0.5 dB: 1 Hz – 44.8 kHz
Frequency response @ 192 kHz, -1 dB: 1 Hz - 80 kHz
THD: -100 dB, < 0.001 %
THD+N: -96 dB, < 0.0015 %
Channel separation: > 110 dB
Maximum output level: +19 dBu
Output: 6.3 mm TRS jack, servo-balanced
Output impedance: 75 Ohm
Output level switchable Hi Gain, +4 dBu, -10 dBV
Output level at 0 dBFS @ Hi Gain: +19 dBu
Output level at 0 dBFS @ +4 dBu: +13 dBu
Output level at 0 dBFS @ -10 dBV: +2 dBV
DA – Phones, 7/8, front
as DA, but:
Output: 6.3 mm TRS jack, unbalanced
Output impedance: 30 Ohm
30.2 MIDI
2 x MIDI I/O breakout cable with 4 x 5-pin DIN jacks
Galvanically isolated by optocoupled input
Hi-speed mode: Jitter and response time typically below 1 ms
Separate 128 byte FIFOs for input and output
30.3 Digital
Clocks: Internal, ADAT In, SPDIF In, word clock in. Optional LTC/Video in
Low Jitter Design: < 1 ns in PLL mode, all inputs
Internal clock: 800 ps Jitter, Random Spread Spectrum
Jitter suppression of external clocks: > 30 dB (2.4 kHz)
Effective clock jitter influence on AD and DA conversion: near zero
PLL ensures zero dropout, even at more than 100 ns jitter
Digital Bitclock PLL for trouble-free varispeed ADAT operation
Supported sample rates: 28 kHz up to 200 kHz
30.4 Digital Inputs
Word Clock
BNC, not terminated (10 kOhm)
Switch for internal termination 75 Ohm
Automatic Double/Quad Speed detection and internal conversion to Single Speed
SteadyClock guarantees super low jitter synchronization even in varispeed operation
Not affected by DC-offsets within the network
Signal Adaptation Circuit: signal refresh through auto-center and hysteresis
Overvoltage protection
Level range: 1.0 Vpp – 5.6 Vpp
Lock Range: 27 kHz – 200 kHz
Jitter when synced to input signal: < 1 ns
Jitter suppression: > 30 dB (2.4 kHz)