User Manual

User’s Guide ADI-2 Pro – v 1.91
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Common interface jitter values in real
world applications are below 10 ns, a
very good value is less than 2 ns.
The screenshot shows an extremely
jittery SPDIF signal of about 50 ns jitter
(top graph, yellow). SteadyClock turns
this signal into a clock with less than 2
ns jitter (lower graph, blue). The signal
processed by SteadyClock is of course
not only used internally, but also used
to clock the digital output. Therefore
the refreshed and jitter-cleaned signal
can be used as reference clock without
hesitation.
The above numbers refer to interface jitter which is measured directly at a word clock output, or
on the digital signal itself. The so called sampling jitter, usually in the range of a few picosec-
onds, is also extremely low on the ADI-2 Pro. One way to show this is to send out a specially
modulated 11.025 kHz sine from the analog output, then analyze the sampled result from the
analog input. Jitter products will be visible in the measurement as symmetrical sidebands, like
narrow needles. The picture below shows such a measurement and analysis using two ADI-2
Pro with one as generator and one as analyser – and no obvious sidebands that could possibly
be audible as jitter. The measurement also shows that the unit behaves absolutely identical
when used with internal or external clock – a typical feature of the SteadyClock technology.