Multi-Channel High Speed Counter (Catalog Number 1746-HSCE2) User Manual
Important User Information Because of the variety of uses for the products described in this publication, those responsible for the application and use of these products must satisfy themselves that all necessary steps have been taken to assure that each application and use meets all performance and safety requirements, including any applicable laws, regulations, codes and standards.
Table of Contents Preface Who Should Use This Manual . . . . . . . . . . . . Purpose of This Manual. . . . . . . . . . . . . . . . . Related Documentation . . . . . . . . . . . . . . Conventions Used In This Manual . . . . . . . . . Your Questions or Comments on the Manual . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . P-1 P-1 P-2 P-3 P-3 Overview ........ ........ ........ ........ ........ ........ ........ ........ ........ ........ .....
Table of Contents ii Counter Types . . . . . . . . . Linear Counter. . . . . . . Ring Counter . . . . . . . . Rate Value . . . . . . . . . . . . Accuracy . . . . . . . . . . . Output Control . . . . . . . . . Range Control. . . . . . . . . . Count Range . . . . . . . . Rate Range . . . . . . . . . Counter Input Data . . . . . . Class 1 Operation . . . . Class 4 Operation . . . . Input Word Bit Values . Output State Byte. . . . . Counter Status Bytes . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents Module Setup Block . . . . . . . . . . . . . . . . . . Programming Block Identification Bit . . . TRMT: Transmit Bit . . . . . . . . . . . . . . . . DEBUG: Debug Mode Selection Bit . . . . INT: Interrupt Enable . . . . . . . . . . . . . . . RVF: Rate Value Format . . . . . . . . . . . . . PRA: Program Range Allocation . . . . . . . Op Mode: Operating Mode . . . . . . . . . . Range Allocation Values. . . . . . . . . . . . . Range Allocation Examples . . . . . . . . . .
Table of Contents iv Counter Control Block. . . . . . . . . . . . . . . Transmit Bit. . . . . . . . . . . . . . . . . . . . Programming Block Identification Bit . Control Words . . . . . . . . . . . . . . . . . . ENn: Enable Counter (n) Bit. . . . . . . . SPn: Soft Preset Only (n) Bit . . . . . . . IDn: Internal Direction (n) Bit . . . . . . C/R(n): Count or Rate Value Bit . . . . . P(n): Program Counter (n) Bit . . . . . . Output ON (OR) Mask . . . . . . . . . . . . Output Enable Mask . . . . . . . . . .
Table of Contents v Example 6 - Retentive Counters . . . . . . . . . . . . . . . . . . . . . 6-23 Data Table for N10 File (hexidecimal). . . . . . . . . . . . . . 6-25 Data Table for N11 File (decimal) . . . . . . . . . . . . . . . . . 6-25 Appendix A Specifications General . . . . . . . . . . . . . . . . Inputs A, B, and Z . . . . . . . . Outputs (sourcing) . . . . . . . . On-State Current Derating Throughput and Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Table of Contents vi Publication 1746-UM002B-EN-P - August 2004
Summary of Changes The information below summarizes the changes to this manual since the last printing. To help you find new information and updated information in this release of the manual, we have included change bars as shown to the right of this paragraph. New Information 1 The table below lists sections that include new information. For this new information See page(s) Note on limitations of rate value calculation at input frequencies below 60 Hz.
2 Summary of Changes Publication 1746-UM002B-EN-P - August 2004
Preface Read this preface to familiarize yourself with the rest of the manual. This preface covers the following topics: • • • • • Who Should Use This Manual who should use this manual how to use this manual related publications conventions used in this manual Rockwell Automation support Use this manual if you are responsible for designing, installing, programming, or troubleshooting control systems that use Allen-Bradley small logic controllers.
2 Preface Related Documentation The table below provides a listing of publications that contain important information about SLC™ products.
Preface Conventions Used In This Manual The following conventions are used throughout this manual: Your Questions or Comments on the Manual If you find a problem with this manual, please notify us. If you have any suggestions for how this manual could be made more useful to you, please contact us at the address below: 3 • Bulleted lists (like this one) provide information, not procedural steps. • Numbered lists provide sequential steps or hierarchical information. • Italic type is used for emphasis.
4 Preface Publication 1746-UM002B-EN-P - August 2004
Chapter 1 Module Overview This chapter contains the following: • multi-channel high-speed counter module overview • operating class • hardware features Multi-Channel High-Speed Counter Module Overview The 1746-HSCE2 is an intelligent counter module with its own microprocessor and I/O that is capable of reacting to high-speed input signals without the intervention of the SLC processor.
1-2 Module Overview Inputs The module features six high-speed differential inputs labeled ±A1, ±B1, ±Z1, ±A2, ±B2, and ±Z2. It supports quadrature encoders with ABZ inputs and/or up to six discrete switches. In addition, x1, x2, and x4 counting configurations are provided to fully use the capabilities of high resolution quadrature encoders. The inputs can be wired for single-ended or differential use. Inputs are opto-isolated from the backplane.
Module Overview 1-3 Most programming parameters, except those in the Module Setup and Counter Configuration blocks, are dynamic and can be changed without halting counter operation. The table below lists the static and dynamic parameters by programming block. Programming Block Parameter Type(1) Operating Mode Module Setup Range Allocation Interrupt Enable Static Rate Value Format Counter Type Counter Configuration Input Configuration Static(2) Gate/Preset Mode Min./Max. Count Value Min./Max.
1-4 Module Overview Operating Class Module operation differs slightly based on the operating class. The operating class is selected via the module ID code. Class 1 Class 1 operation is compatible with all SLC 500 processors. In Class 1 operation, the module uses 8 input and 8 output words and has an associated ID code of 3511. A maximum of four 16-bit counters are available in this operating class. Class 4 Class 4 operation is compatible with SLC 5/03 and above systems.
Module Overview Hardware Features 1-5 The module’s hardware features are illustrated below. Refer to Chapter 3 for detailed information on installation and wiring. Figure 1.1 Hardware Features COUNTER Output Status LEDs OUTPUT STATUS Input Status LEDs 0 1 2 A1 B1 Z1 3 RUN A2 B2 Z2 FLT INPUT STATUS Running Status LED Fault Status LED HSCE2 Input and Output Terminals LEDs The front panel has a total of twelve indicator LEDs, as shown in Figure 1.1 on page 1-5.
1-6 Module Overview Jumpers Six jumpers select the input voltages for the six inputs A1, B1, Z1, A2, B2, and Z2. The module accepts input voltages of 5V dc, 12V dc, or 24V dc. See Chapter 3 for jumper locations and settings.
Chapter 2 Module Operation The chapter contains information about: • • • • • • • Operating Modes operating modes input configurations gate/preset modes counter types rate value outputs range types The module’s operating mode determines the number of available counters and which inputs are attached to them. The three operating modes and their input assignments are summarized in Figure 2.1. Figure 2.
2-2 Module Operation Input Configurations Input configurations determine how the A and B inputs cause the counter to increment or decrement. The six available configurations are: • • • • • • Pulse/External Direction Pulse/Internal Direction Up and Down Pulses X1 Quadrature Encoder X2 Quadrature Encoder X4 Quadrature Encoder See the Summary of Available Counter Configurations on page 2-8 for the input configurations available for the counters, based on operating mode.
Module Operation 2-3 Pulse/Internal Direction When the Pulse/Internal Direction configuration is selected, a bit written from the backplane determines the direction of the counter. The counter increments on the rising edge of the input if the bit is low (0) and decrements on the rising edge of the input if the bit is high (1). Up and Down Pulses In this configuration, the counter increments on the rising edge of pulses applied to input A and decrements on the rising edge of pulses applied to input B.
2-4 Module Operation X1 Quadrature Encoder When a quadrature encoder is attached to inputs A and B, the count direction is determined by the phase angle between inputs A and B. If A leads B, the counter increments. If B leads A, the counter decrements. The counter changes value only on one edge of input A as shown in Figure 2.4 on page 2-5. TIP If B is low, the count increments on the rising edge of input A and decrements on the falling edge of input A.
Module Operation 2-5 Figure 2.4 Quadrature Encoder Configurations A Input A B Input B Z Quadrature Encoder Input Z Reverse Rotation Forward Rotation A B 1 2 3 2 1 0 X1 Count 1 2 3 4 5 6 5 4 3 2 1 0 X2 Count 1 2 3 4 5 6 7 8 9 10 11 12 11 10 9 8 7 6 5 4 3 2 1 0 X4 Count IMPORTANT Input Frequency The input configuration is limited by the operating mode. In mode 1, Counters 1 and 2 can be assigned any input configuration.
2-6 Module Operation Gate/Preset Modes A counter’s gate/preset mode determines what, if any, gating is applied to the counter and what, if any, conditions will preset the counter to the preset value. The Z inputs are the only inputs used for gating or presetting. The six gate/preset modes are described below. No Preset The counter is not preset under any conditions. The Z inputs are not used.
Module Operation 2-7 Store/Hold/Resume counter has stopped counting resume counting stop count store count The count value, captured when the module detects a positive transition on the Z input, is made available to the backplane. A stored status bit is set in the input image table to signal the processor that a new value is available. This bit is active until the capture value is read by the processor.
2-8 Module Operation Gate and Preset Limitations Because only the Z inputs are used for external gating and presetting, the only gate/preset modes available for Counters 3 and 4 are No Preset and Soft Preset Only. All six modes are always available for Counters 1 and 2. IMPORTANT In Class 1, Operating Mode 2, Counter 2 does not have a capture value available. In Class 1, Operating Mode 3, no capture values are available.
Module Operation Counter Types 2-9 Each counter can be programmed to operate as a linear or ring counter. Both types are described below. Linear Counter The figure below demonstrates linear counter operation. In linear operation, the count value must remain within the programmed minimum/maximum values. If the count value goes above or below these values, the counter stops counting, and an overflow/underflow bit is set.
2-10 Module Operation Ring Counter Figure 2.6 demonstrates ring counter operation. In ring counter operation, the count value changes between programmable minimum and maximum values. If, when counting up, the counter reaches the maximum value, it rolls over to the minimum value. If, when counting down, the counter reaches the minimum value, it rolls over to the maximum value. Figure 2.
Module Operation 2-11 Additional checks ensure that rates below 1 Hz, which are not supported by the module, and frequencies due to motor vibration, are not counted in the rate value calculation. Table 2.
2-12 Module Operation Range Control The module can be programmed to use either counter or rate ranges to determine whether an output is active. Up to 16 dynamically configurable ranges are available. The ranges, programmed using range start and range stop values, can overlap. When the count is within more than one range, the output patterns of those ranges are combined (logically ORed) to determine the actual status of the output. A mixture of count ranges and rate ranges may be used.
Module Operation 2-13 Figure 2.8 Count Range with Ring Counter Range 3 32,000 500 200 1 Range 2 32,767 23,000 8,000 Range 4 20,000 10,000 12,500 Range 1 Outputs(1) Start Value Stop Value 7 6 5 4 3 2 1 0 Outputs Affected 1 10,000 12,500 0 0 0 0 0 0 0 1 0 2 200 8,000 0 0 0 0 0 0 1 0 1 3 32,000 500 0 0 0 0 0 1 0 0 2 4 20,000 23,000 0 0 0 0 1 0 0 1 0 and 3 Range (1) Bits 0 through 3 are real outputs. Bits 4 through 7 are virtual outputs.
2-14 Module Operation Rate Range In a rate range, the outputs are active if the rate measurement is within the user-defined range. The valid input rate is dependent upon the operating class. In Class 1, the input rate can be up to 32,767 Hz in either direction. In Class 4, the input rate can be up to 1 MHz in either direction. The linear counter example in Figure 2.9 uses Class 1 operation. Figure 2.9 Rate Range -32,767 (min. rate value) 0 +32,767 (max.
Module Operation 2-15 Class 1 Operation In this operating class, the input data consists of eight words. The counters are sixteen bits. The data stored in an input word change based on the module’s operating mode. Figure 2.
2-16 Module Operation Class 4 Operation In Class 4 operation, the counter data consist of a maximum of 23 words. Figure 2.
Module Operation 2-17 Input Word Bit Values ACK: Acknowledge Bit This bit makes a 0 to 1 transition to signal the receipt of programming data. MFLT: Module Fault Bit This bit is set only if the module does not power up correctly. After a proper power up, the MFLT bit remains reset. PERR: Programming Error Bit The state of this bit is valid only when the acknowledge bit is set. This bit is reset when the last programming block is accepted without error.
2-18 Module Operation OP MODE: Operating Mode Bits The module uses these two bits to tell the processor what mode it is in. In class 1, the data value that an input word contains changes based on the operating mode. Table 2.2 Mode Bit Settings Bit 09 Bit 08 Mode 0 0 Reserved 0 1 Mode 1 1 0 Mode 2 1 1 Mode 3 Output State Byte These bits correspond to the real or virtual state of the outputs. Bits 00 through 03 represent real outputs. Bits 04 through 07 represent virtual outputs.
Module Operation 2-19 C/R: Count/Rate Bit The count/rate bit is used only in Class 1 operating mode. Because only one data word is available for Counters 2 and 3 in operating mode 2, and one data word for each of the four counters in operating mode 3, the module transfers either the counter’s count or rate value. When this bit is reset (0), the data in the corresponding word is the count value. When this bit is set (1), the data in the corresponding word is the rate value.
2-20 Module Operation Publication 1746-UM002B-EN-P - August 2004
Chapter 3 Installation and Wiring This chapter provides the following information: • • • • • • Compliance to European Union Directives compliance to European Union Directives module installation wiring considerations input/output connections encoder wiring switch wiring If this product has the CE mark, it is approved for installation within the European Union and EEA regions. It has been designed and tested to meet the following directives.
3-2 Installation and Wiring For specific information required by EN61131-2, see the appropriate sections in this publication, as well as the following Allen-Bradley publications: • Industrial Automation, Wiring and Grounding Guidelines for Noise Immunity, publication 1770-4.1 • Automation Systems Catalog, publication B111 Prevent Electrostatic Discharge ATTENTION ! Static discharges may cause permanent damage to the module.
Installation and Wiring 3-3 Figure 3.1 Jumper Settings JP1 (A1 ) JP2 (B1) JP3 (Z1) JP4 (A2) JP5 (B2) JP6 (Z2) Jumper Settings 5V dc 4.2-12V dc 24V dc 10-30V dc (default) IMPORTANT For a 12V dc encoder signal, use the 24V dc jumper setting. ATTENTION If jumpers are not set to match the encoder type, the module may be damaged. ! The 5V dc settings respond to inputs with an active voltage between 4.2 and 12 volts.
3-4 Installation and Wiring 1. Make sure your SLC power supply has adequate reserve current capacity. The module requires 250 mA at +5V dc. 2. Align the full-sized circuit board with the chassis card guide as shown in Figure 3.2. The first slot of the first chassis is reserved for the processor. 3. Slide the module into the chassis until the top and bottom latches catch. To remove the module, press the release clips at the top and bottom of the module and slide it out. 4.
Installation and Wiring 3-5 • Shields should be grounded only at one end. Ground the shield wire outside the module at the chassis mounting screw. Connect the shield at the encoder end only if the housing is electronically isolated from the motor and ground. Figure 3.3 Grounding the Shield Wire at the Chassis Mounting Screw Spade Connector Chassis Mounting Tab Mounting Screw Star Washer • If you have a junction in the cable, treat the shields as conductors at all junctions.
3-6 Installation and Wiring Electronic Protection The electronic protection of the 1746-HSCE2 has been designed to provide protection for the module from overload current conditions. The protection is based on a thermal cut-out principle. In the event of a short circuit or overload current condition on an output channel, all channels will turn off within milliseconds after the thermal cut-out temperature has been reached.
Installation and Wiring Input and Output Connections 3-7 Input and output wiring terminals are shown in the figure below. Each terminal accepts #14 AWG wire. Tighten screws only tight enough to immobilize the wire. The torque applied to the screw should not exceed 0.9 Nm (8 in-lb.). Figure 3.
3-8 Installation and Wiring Encoder Wiring Differential encoders provide the best immunity to electrical noise. We recommend, whenever possible, to use differential encoders. The wiring diagrams on the following pages are provided to support the Allen-Bradley encoders you may already own. Differential Encoder Wiring Figure 3.
Installation and Wiring 3-9 Single-Ended Encoder Wiring (Open Collector) Figure 3.7 Single-Ended Encoder Wiring Cable(1) VS +VDC GND COM R Power Supply (2) A1(+) A A1(–) B Allen-Bradley 845H Series single-ended encoder B1(+) B1(–) Z1(+) Z Z1(–) Shield shield/housing Connect only if housing is electronically isolated from the motor and ground. Earth Module Inputs (1) Refer to your encoder manual for proper cable type.
3-10 Installation and Wiring Single-Ended Wiring (Discrete Devices) Figure 3.
Chapter 4 Configuration and Programming This chapter provides information about: • • • • Selecting Operating Class selecting operating class module programming programming blocks programming block default values The 1746-HSCE2 module has two operating classes which are determined by the ID code used by the module. Class 1 operation uses 8 input and 8 output words and is compatible with SLC 5/01 and above processors and the 1747-ASB module. Enter ID Code 3511 to select Class 1 operation.
4-2 Configuration and Programming Each block is made up of eight words. The first word is the control word. The remaining seven words are data words. The control word determines which parameters are in the data words. This programming method applies to both classes of operation. The programming blocks are described on pages 4-6 through 4-23. Programming Cycle Except for the Counter Control Block, all programming blocks are written to the module with a programming cycle.
Configuration and Programming 4-3 Data Format In Class 4, the counter accepts rate data in either integer or floating-point data formats, depending upon the setting of the rate value bit. Both formats are explained below. TIP Count values are always in integer format. The format of rate values is selected in the Module Setup Block as either integer or floating-point formats. All other data is in integer format.
4-4 Configuration and Programming Reading the Data In the following example, the 1746-HSCE2 module is located in slot 3. The rate value, in floating point rate value format, is located in input data file words 4 and 5 (I:3.4 and I:3.5). To view the rate value for counter 1, use the copy instruction as shown below. COP Copy File Source Dest Length #I:3.4 #F8:1 1 The source is the input data file, and the destination is the floating point file.
Configuration and Programming 4-5 Converting from Floating-Point to Two-word Integer Format RSLogix500 programming software can also be used to convert from floating-point to two-word integer format as shown. F8:4 holds the number to be converted. It is divided by 1000 and the result is placed in F8:3. TWO-WORD 1 TEMP DIV Divide Source A F8:4 0.0 < Source B 1000.0 1000.0 < Dest F8:3 0.0 < 0001 The value in F8:3 is moved to N7:34, yielding the upper word (Most Significant Word - MSW).
4-6 Configuration and Programming Module Setup Block Figure 4.1 shows the format of the Module Setup block. This block sets the module’s basic configuration and range allocation to the counters. Counters cannot be running when this block is sent to the module or a programming error results. Sending this block to the module sets all other module parameters to their default values. See Programming Block Default Values on page 4-28. Figure 4.
Configuration and Programming 4-7 INT: Interrupt Enable (Word 1, Bit 10) IMPORTANT Interrupt mode is not available in Class 1. Setting this bit while using Class 1 causes a programming error. In Class 4, when this bit is set (1), the module generates an I/O interrupt to the SLC processor whenever one of the eight outputs changes state. When this bit is reset (0), the module will not generate an interrupt. IMPORTANT An I/O interrupt must be defined if the INT bit is set.
4-8 Configuration and Programming Op Mode: Operating Mode (Word 1, Bits 01 and 00) These two bits program the module’s operating mode. The combinations are shown below: Table 4.2 Operating Mode Programming Bit Settings Bit 01 Bit 00 Operating Mode 0 0 Reserved(1) 0 1 Mode 1 1 0 Mode 2 1 1 Mode 3 (1) Using the reserved setting causes a programming error. Range Allocation Values (Words 2, 3, and 4, Bits 00 to 04) Sixteen ranges are available for programming output on/off positions and rates.
Configuration and Programming 4-9 Range Allocation Examples Mode 1 Example In the Module Setup block below, 4 ranges are assigned to Counter 1. The remaining 12 are assigned to Counter 2. The last counter is not specified. Figure 4.
4-10 Configuration and Programming Mode 3 Example In the Module Setup block below, four ranges are assigned to Counter 1. Eight ranges are assigned to Counter 2. Two ranges are assigned to Counter 3. The last two ranges are assigned to Counter 4, but the counter is not specified. The number of ranges for the last configured counter used must equal zero, otherwise the module fills in the value and errors, even if the value is correct. IMPORTANT Figure 4.
Configuration and Programming 4-11 Figure 4.
4-12 Configuration and Programming PGMn: Program Counter Number Bits (Word 0, Bits 08 to 11) These four bits select the counters to which the programming block is applied. If the bit is reset, the associated counter is not programmed and the counter can be running when this block is sent. In addition, the associated programming words must be zero or a programming error occurs. A counter must be stopped when programmed with this block.
Configuration and Programming 4-13 G/P Mode: Gate/Preset Mode Bits (Words 1 and 3, Bits 04 to 06; Word 5, Bits 09 and 01) Counters 3 and 4 have only two gate/preset modes available. Therefore, they have only one G/P mode bit. When this single bit is equal to zero, the No Preset mode is selected. When the bit is set, the Soft Preset mode is selected. Three bits determine the Gate/Preset Mode for Counters 1 and 2. The table below shows the G/P Mode settings for counters 1 and 2. Table 4.
4-14 Configuration and Programming Figure 4.
Configuration and Programming 4-15 CNTR No.: Counter Number Bits (Word 0, Bit 08 and 09) These two bits select the counter to which this programming block is applied. Table 4.6 Counter Number Bit Settings Bit 09 Bit 08 Counter Number 0 0 Counter 1 0 1 Counter 2 1 0 Counter 3 1 1 Counter 4 Preset Value (Words 5 and 6) The preset value can be programmed to any number between the minimum count value and the maximum count value.
4-16 Configuration and Programming always included with this block, and its value must fall between the minimum/maximum count values. The data is in the two-word integer format as described in Integer Format on page 4-3. Counter Type The meanings of the minimum and maximum counter values are dependent on the counter type. Ring Counter As a ring counter, the counter counts between the minimum and maximum values.
Configuration and Programming 4-17 Figure 4.7 Min./Max. Rate Value Block 0 Word 1 Word 2 Word 3 Word 4 0 DEBUG Word 0 TRMT 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 CNTR No. 0 0 0 0 1 0 0 0 Minimum Rate Value in integer or floating point notation Maximum Rate Value in integer or floating point notation Word 5-7 RESERVED: Must equal zero Programming Block Identification Bit (Word 0, Bit 03) This bit identifies the type of block.
4-18 Configuration and Programming CNTR No.: Counter Number Bits (Word 1, Bits 08 and 09) These two bits select the counter to which this programming block is applied. Table 4.8 Counter Number Bit Settings Bit 09 Bit 08 Counter Number 0 0 Counter 1 0 1 Counter 2 1 0 Counter 3 1 1 Counter 4 Minimum/Maximum Rate Value Words (Words 1 to 4) The valid range of this parameter is dependent on the operating class of the module.
Configuration and Programming 4-19 Class 4 When the module is operating as Class 4, the data format of the minimum/maximum rate values is determined by the rate value format bit in the Module Setup programming block. When this bit specifies that the rate value be in floating-point format, the minimum/maximum rate values are also programmed in floating-point format. When the rate value format bit specifies integer format, the minimum/maximum rate value is also in two-word integer format.
4-20 Configuration and Programming Figure 4.8 Program Ranges Block 0 0 RType 0 DEBUG Word 0 TRMT 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Word 1 0 0 0 1 0 0 0 0 Range Number Word 2 Range Start Value Word 3 Word 4 Range Stop Value Word 5 Word 6 CNTR No 0 0 0 Word 7 0 0 0 0 0 Output State Virtual Real RESERVED: Must equal zero Programming Block Identification Bit (Word 0, Bit 04) This bit identifies the type of block.
Configuration and Programming 4-21 CNTR No.: Counter Number Bits (Word 0, Bits 08 and 09) These two bits select the counter to which this programming block is applied. The counter number and range number must correspond to a valid combination as determined by the information in the Module Setup Block. See Range Allocation Values on page 4-8. Table 4.
4-22 Configuration and Programming The range number word is subject to the following special conditions: • If the range start value equals the range stop value and word 6 equals zero, the range indicated is reset. • If a range or ranges not belonging to the indicated counter are set, the block is rejected and a programming error results. • If the range number equals zero and words two through 7 are equal to zero, all ranges associated with the counter are reset.
Configuration and Programming 4-23 Output State on page 4-27 for a description of how the bytes are combined. If the start value is less than the stop value, the output state is applied when the count or rate is within the range specified by the two values. (For example, see ranges 1 through 3 on page 2-13.) If the start value is greater than the stop value, the output state is applied when the count or rate is outside the range. (For example, see range 4 on page 2-13.
4-24 Configuration and Programming Transmit Bit The transmit bit is not used. A programming cycle is not needed to program these bits. The block is acted upon for every program scan that bit 07 of word 0 is set. Therefore, a transmit bit is not used. TIP If an invalid condition exists, the PERR and ACK bits are set and all data in the block is considered invalid. Programming Block Identification Bit (Word 0, Bit 07) This bit identifies the type of block.
Configuration and Programming 4-25 counter must also be disabled before sending new minimum/maximum count values. TIP Disabling a counter does not cause an output with the counter to turn off. As long as the count value is within the programming range the output remains active. TIP Enabling a counter that is not present causes a programming error.
4-26 Configuration and Programming C/R(n): Count or Rate Value Bit (Words 1 to 4, Bit 08) These bits are only used when the module is configured for Class 1 operation. Depending on the operating mode, the module only transmits the counter’s count or rate value. The count value is transmitted when the C/R(n) bit is reset. The rate value is transmitted when the C/R(n) bit is set. When configured for Class 4, setting these bits generates a programming error.
Configuration and Programming 4-27 output turns on based on the programmed ranges, the state of the enabled ranges byte, and the Output ON Mask. TIP The outputs do not turn on if the corresponding bits are not set here. Enable Range (Word 6) When a bit in this word is reset (0), the corresponding range (1-16) is disabled, and the output state for the range is ignored. When a bit in this word is set (1), the corresponding output state for the range is used to determine the state of the eight outputs.
4-28 Configuration and Programming Figure 4.10 Determining Actual Outputs Programming Block Default Values Range Bit Setting 1 1 0 0 1 1 0 0 Output ON Mask 0 0 0 1 0 0 0 1 Output Enable Mask 0 0 0 0 1 1 1 1 Actual Outputs 0 0 0 0 1 1 0 1 The following tables list the default values for all of the programmed parameters in each class and operating mode. The default operating mode for each class is mode 1. Class 1 Table 4.
Configuration and Programming 4-29 Table 4.
4-30 Configuration and Programming Class 4 Table 4.
Configuration and Programming 4-31 Table 4.
4-32 Configuration and Programming Publication 1746-UM002B-EN-P - August 2004
Chapter 5 Start Up, Operation, Troubleshooting, and Debug Mode This chapter provides start up, operation, and troubleshooting information, as well as detailing the operation of the debug mode. Start Up The following steps will assist you in the start up of your 1746-HSCE2 module. 1. Install the module in the chassis. 2. Wire the input and output devices. 3. Configure and program your SLC processor to operate with the module. 4. Apply power to the SLC system and to the attached inputs and outputs.
5-2 Start Up, Operation, Troubleshooting, and Debug Mode Figure 5.1 LED Locations COUNTER Output Status OUTPUT STATUS 1 2 3 0 A1 Input Status B1 Z1 A2 B2 Z2 INPUT STATUS RUN FLT Running Status Fault Status HSCE2 Troubleshooting Three types of module-generated errors can occur: • module diagnostic errors • module programming errors • application errors. The Fault LED indicates a module diagnostic error. Fault LED Problem Solid Red Module diagnostic error. Cycle power.
Start Up, Operation, Troubleshooting, and Debug Mode 5-3 Module Programming Errors A programming error is caused by improper set up of a module parameter. The module responds to a programming error by setting the programming error bit. When this bit is set, the entire programming block is rejected. The programming error bit is set when a reserved bit is set. It is also set under the following conditions: Table 5.
5-4 Start Up, Operation, Troubleshooting, and Debug Mode Table 5.1 Error Conditions by Programming Block Programming Block Min./Max. Rate Value Error Conditions • Counter number bits are not set to a valid number. (Operating Mode may be incorrect.) • The minimum rate is outside its valid range. • The maximum rate is outside its valid range. • The maximum rate is less than or equal to the Minimum Rate. • Programmed output rate ranges are outside the boundaries of the new minimum/maximum rate values.
Start Up, Operation, Troubleshooting, and Debug Mode 5-5 The rate underflow bit is set when the rate value is less than the minimum rate value. When the module is in overflow condition, the programmed maximum rate value is reported and ranges that include the value will still be acted upon. Likewise, in underflow condition, the minimum rate value is reported, and ranges including it are affected.
5-6 Start Up, Operation, Troubleshooting, and Debug Mode Output Does Not Turn Off Check the associated module LED for the output. If the LED is illuminated, check your program operation. If the LED is not illuminated, check the wiring to your output device. Check the leakage current of your connected device. Soft Preset Does Not Work Soft preset does not work when the counter’s P(n) bit is changed from 1 to 0 to 1 at the same time that the SP(n) bit is changed from 1 to 0 to 1.
Start Up, Operation, Troubleshooting, and Debug Mode 5-7 due to their unpredictable nature. Even if the configuration block looks satisfactory in the N10 data file, the data block in the module’s output image may not be satisfactory. The best way to check for this problem is to individually search the ladder logic program for all module output words (O:e.0, O:e.1, etc.).
5-8 Start Up, Operation, Troubleshooting, and Debug Mode Figure 5.3 Required Bits for Module Setup and Counter Configuration Blocks 0 DEBUG Word 0 TRMT 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 0 0 0 0 0 BLOCK TYPE The debug view of this block shows the range allocation of all four counters. The fourth counter is shown in word 5. The PRA bit (word 0, bit 08) is never set.
Start Up, Operation, Troubleshooting, and Debug Mode 5-9 In the Minimum/Maximum Rate Value Block For this block, the transmit bit, the debug bit, the block type byte, and the counter number are required for each configured counter. Word 0 must be used for each configured counter individually. Bits 10, 11, 13, and 14 must be zero. The values of words 1 through 7 are ignored by the module while in debug mode. Figure 5.6 Required Bits for Min./Max.
5-10 Start Up, Operation, Troubleshooting, and Debug Mode EXAMPLE Activating Debug Mode 1. Clear the output image table. 2. Set the required bits in the block that will be echoed back. 3. Set the debug mode bit. 4. Set the transmit bit. Once the steps above are complete, you can reference the input image words to reflect the block’s configuration. NOTE: Only the first eight words in the input image have meaning in Class 4.
Chapter 6 Application Examples This chapter contains the following application examples: • Example 1 uses the 1746-HSCE2 in Class 1, mode 3 to count four single-ended, high-speed pulse train inputs using direct addressing only (SLC 5/01™ or SLC 5/02™). • Example 2 tracks counts and speeds from two quadrature encoders with indirect addressing (SLC 5/03™ and above). The module is used in Class 4, mode 1.
6-2 Application Examples Example 1 - Direct Addressing This example sets up the module to count the number of pulses from a high-speed device and apply that information to your ladder program. The module is in Class 1, mode 3, with 4 counters available.
Application Examples 6-3 Ladder File 9 - HSCE2 Initialization Routine Programming ladder file 9 shows the direct addressing required to set up the programming blocks in this example. Copy Module Setup Block to the HSCE2 and set transmit bit. DATA_BLOCK_PTR 0000 EQU EQU Equal Source A Source B HSCE2_XMIT O:1 N11:0 140< 0 0< 15 1746-HSCE2 HSCE2_ACK I:1 COP COP Copy File Source Dest Length 15 1746-HSCE2 #N10:0 #O:1.
6-4 Application Examples Ladder File 9 Continued When the previous block is completed (transmit and acknowledge bit are reset), copy Min/Max Count Value Block for counter 3 to the HSCE2 and set transmit bit (O:e.0/15). 0004 DATA_BLOCK_PTR EQU EQU Equal Source A N11:0 140< Source B 40 40 < HSCE2_XMIT O:1 15 1746-HSCE2 HSCE2_ACK I:1 15 1746-HSCE2 COP COP Copy File Source Dest Length #N10:40 #O:1.
Application Examples 6-5 Ladder File 9 Continued When the previous block is completed (transmit and acknowledge bit are reset), copy Programming Ranges Block 4 for counter 1 to the HSCE2 and set transmit bit (O:e.0/15). 0008 DATA_BLOCK_PTR EQU EQU Equal Source A N11:0 140< Source B 80 80 < HSCE2_XMIT O:1 15 HSCE2_ACK I:1 15 1746-HSCE2 1746-HSCE2 COP COP Copy File Source Dest Length #N10:80 #O:1.
6-6 Application Examples Ladder File 9 Continued When the previous block is completed (transmit and acknowledge bit are reset), copy Programming Ranges Block 8 for counter 1 to the HSCE2 and set transmit bit (O:e.0/15). 0012 DATA_BLOCK_PTR EQU EQU Equal Source A N11:0 140< Source B 120 120< HSCE2_XMIT O:1 15 1746-HSCE2 HSCE2_ACK I:1 COP COP Copy File Source #N10:120 Dest #O:1.
Application Examples 6-7 Data Table for N10 File (hexidecimal) Programming Blocks Module Setup Counter Configuration Min/Max Count Value Counter 1 Min/Max Count Value Counter 2 Min/Max Count Value Counter 3 Min/Max Count Value Counter 4 Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Counter Control Offset N10:0 N10:10 N10:20 N10:30 N10:40 N10:50 N10:60 N10:70 N10:80 N10:90 N10:100 N10:110 N10:120 N10:130 N10:140 N10:150 0 1 F02 4 1
6-8 Application Examples Ladder File 8 - HSCE2 Prior to use, the programmer sets N11:2 to the total number of data blocks which will be entered into file N10 (not including the Counter Control Block), adds one rung for each configuration block (including the Counter Control Block), and initializes the data blocks in file N10. Ten integer data blocks are used (instead of eight) to simplify the display in data windows.
Application Examples 6-9 Ladder File 9 - HSCE2 Initialization Routine Programming ladder file 9 shows the indirect addressing required to set up the programming blocks in this example. If the blocks have not all been transmitted (block data offset < max block offset), copy block to the HSCE2 and set transmit bit (O:e.0/15).
6-10 Application Examples Data Table for N10 File (hexidecimal) Programming Blocks Module Setup Counter Configuration Min/Max Count Value Counter 1 Min/Max Count Value Counter 2 Min/Max Rate Value Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Counter Control Offset N10:0 N10:10 N10:20 N10:30 N10:40 N10:50 N10:60 N10:70 N10:80 N10:90 N10:100 N10:110 N10:120 N10:130 N10:140
Application Examples 6-11 addresses (e.g., I:1.0) have been replaced with block transfer data file addresses (e.g., N12:0). TIP The only changes necessary to permit a different 1746-HSCE2 configuration are to the data files N10 and N11.
6-12 Application Examples Ladder File 8 Continued Continuously re-trigger 8-word block transfers to the remote HSCE2. BT20:1 BTW Block Transfer Write Module Type Generic Block Transfer Rack 001 Group 0 Module 0 Control Block BT20:1 Data File N12:10 Length 8 Continuous No 0001 EN EN DN ER Continuously re-trigger 8-word block transfers to the remote HSCE2.
Application Examples 6-13 Ladder File 9 - HSCE2 Initialization Routine Programming ladder file 9 shows the block transfer function required to set up the programming blocks in this example. If the blocks have not all been transmitted (block data pointer < max block offset), copy next block to the HSCE2 and set transmit bit (N12:10/15).
6-14 Application Examples Data Table for N10 File (hexidecimal) Programming Blocks Module Setup Counter Configuration Min/Max Count Value Counter 1 Min/Max Count Value Counter 2 Min/Max Count Value Counter 3 Min/Max Count Value Counter 4 Counter 1 Program Ranges Counter 1 Program Ranges Counter 1 Program Ranges Counter 1 Program Ranges Counter 1 Program Ranges Counter 1 Program Ranges Counter 1 Program Ranges Counter 1 Program Ranges Counter Control Offset N10:0 N10:10 N10:20 N10:30 N10:40 N10:50 N10:60
Application Examples 6-15 5. The example assumes that the controller control block is in the HSCE2 output image when the soft preset is implemented. Additional logic (for example, preset change latch XIO from example 5) is needed to delay the soft preset logic if other ladder logic changes the output image. (For example, example 5 dynamically changes the preset values and temporarily puts the min/max count value block in the output image.) 6. Rung 3 unlatches the HSCE2 Counter 1 soft preset bit (O:1.
6-16 Application Examples Ladder File 8 - HSCE2 Prior to use, the programmer sets N11:2 to the total number of data blocks which will be entered into file N10 (not including the Counter Control Block) and initializes the data blocks in file N10. Ten integer data blocks are used (instead of eight) to simplify the display in data windows. The first pass of the program initializes the following values: 1. The HSCE2 initialization done bit (B3/0) is unlatched. 2. The HSCE2 error bit (B3/1) is cleared. 3.
Application Examples 6-17 Ladder File 8 Continued This rung implements a soft preset of counter 1 when the soft preset trigger bit sees a positive change (0 to 1). The rung assumes that the Counter Control Block (last configuration block) is still in the output image to the 1746-HSCE2, and that Counter 1 permits soft presets. HSCE2_INIT_DONE B3:0 SOFT_PRESET_TRGR B3:0 SOFT_PRESET_OSR B3:0 OSR 7 0002 0 6 After the soft preset is complete, unlatch the soft preset bit (O:1.1/1).
6-18 Application Examples Data Table for N10 File (hexidecimal) Programming Blocks Module Setup Counter Configuration Min/Max Count Value Counter 1 Min/Max Count Value Counter 2 Min/Max Rate Value Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Counter Control Offset N10:0 N10:10 N10:20 N10:30 N10:40 N10:50 N10:60 N10:70 N10:80 N10:90 N10:100 N10:110 N10:120 N10:130 N10:140
Application Examples 6-19 4. Data word N10:11 was changed from 000C (hex) to 001C (hex) to change the Counter 1 gate/preset mode from No Presets (000) to Soft Presets Only (001). Ladder File 8 - HSCE2 Prior to use, the programmer sets N11:2 to the total number of data blocks which will be entered into file N10 (not including the Counter Control Block) and initializes the data blocks in file N10. Ten integer data blocks are used (instead of eight) to simplify the display in data windows.
6-20 Application Examples Ladder File 8 Continued This rung triggers a dynamic change of the Counter 1 preset. The preset trigger bit (B3/2) sets the preset change latch bit (B3/4). The preset change latch bit (B3/4) remains latched until the Counter Control Block is restored to the 1746-HSCE2 output image. Use B3/4 to ensure that other logic (soft presets) do not write to the output image until the Counter Control Block is restored.
Application Examples 6-21 Ladder File 14 - Preset Change Subroutine Copy the new preset value (N7:0 and N7:1) into counter 1’s min/max count block (N10:25 and N10:26). Copy this block into the 1746-HSCE2 output image, and set the 1746-HSCE2 transmit bit (O:1.0/15). HSCE2_XMIT O:1 HSCE2_ACK I:1 15 OTHER 15 OTHER PRESET_ENABLE B3:0 COP Copy File Source Dest Length 0000 5 #N7:0 #N10:25 2 #HSCE2_CFG_BLK COP Copy File Source #N10:20 Dest #O:1.
6-22 Application Examples Data Table for N10 File (hexidecimal) Programming Blocks Module Setup Counter Configuration Min/Max Count Value Counter 1 Min/Max Count Value Counter 2 Min/Max Rate Value Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Program Ranges Counter Control Offset N10:0 N10:10 N10:20 N10:30 N10:40 N10:50 N10:60 N10:70 N10:80 N10:90 N10:100 N10:110 N10:120 N10:130 N10:140
Application Examples Example 6 - Retentive Counters 6-23 The 1746-HSCE2 configuration and count values are not retentive. If power is cycled to the chassis, the module must be re-initialized and the count value re-entered (preset) if desired. To simulate a retentive counter, the 1746-HSCE2 count values can be read by the processor and “stored” in the Min/max Count Value Block preset value.
6-24 Application Examples Ladder File 8 - HSCE2 Prior to use, the programmer sets N11:2 to the total number of data blocks which will be entered into file N10 (not including the Counter Control Block) and initializes the data blocks in file N10. Ten integer data blocks are used (instead of eight) to simplify the display in data windows. The first pass of the program initializes the following values: 1. The HSCE2 initialization done bit (B3/0) is unlatched. 2. The HSCE2 error bit (B3/1) is cleared. 3.
Application Examples 6-25 Ladder File 9 - HSCE2 Initialization Routine See the ladder logic from Example 2 on page 6-9.
6-26 Application Examples Publication 1746-UM002B-EN-P - August 2004
Appendix A Specifications General 1 Operating Temperature 0°C to +60°C (+32°F to +140°F) Storage Temperature -40°C to +85°C (-40°F to 185°F) Humidity 5 to 95% without condensation Backplane Current Consumption (power supply loading) 250 mA at +5V dc 0 mA at +24V dc Backplane Isolation 1000V dc Maximum Cable Length 300m (1000 ft.
A-2 Specifications Inputs A, B, and Z Input Voltage 5V dc 24V dc Input Voltage Range 4.2V dc to 12V dc 10V dc to 30V dc On-State Voltage (min.) 4.2V 10V Off-State Voltage (max.) 0.8V 3V Maximum Off-state Leakage Current 100 µA 100 µA Input Current (max.) 8 mA 20 mA Input Current (min.) 6.3 mA 6.3 mA Nominal Input Impedance 500 Ω 1500 Ω Min. Pulse Width 475 ns 475 ns Min. Phase Separation 200 ns 200 ns Max.
Specifications A-3 Maximum On-State Current (per module) On-State Current Derating 2.0 A 1.5 A 1.0 A 0.5 A 0˚C 20˚C 40˚C 60˚C Temperature Throughput and Timing Timing (µs) Operation Description Minimum Typical Maximum Throughput The delay between the time the module receives a pulse and when its real outputs and the SLC backplane are updated (based on a count range).
A-4 Specifications Publication 1746-UM002B-EN-P - August 2004
Appendix B Connecting a Differential Encoder This appendix describes the wiring procedures for connecting a differential encoder to the 1746-HSCE2 module. For proper module operation, wire the encoder so that the Z input signal is high (true) at the same time the A and B input signals are low (false). If this condition is not met, inconsistent homing may occur. If you are using an Allen-Bradley Bulletin 845H differential encoder, this condition is met by following the wiring diagrams in the manual.
B-2 Connecting a Differential Encoder 4. Look at the A input signal and its complement A signal. Whichever signal is low for at least part of the marker interval should be wired to the A(+) terminal. If both signals meet this condition, then either signal may be wired to the A(+) terminal. Wire the remaining signal to the A(-) terminal. 5. Since the encoder may be mounted on either end of a motor shaft, the encoder may spin clockwise or counter-clockwise for a given shaft direction.
Appendix C Module Programming Quick Reference The module programming blocks are duplicated below for your reference. A column has been added to show corresponding hex values. Figure C.
C-2 Module Programming Quick Reference Figure C.
Module Programming Quick Reference C-3 Figure C.
C-4 Module Programming Quick Reference Publication 1746-UM002B-EN-P - August 2004
Appendix D Frequently Asked Questions This appendix presents some of the more commonly asked questions about application and operation of the Multi-channel High Speed Counter Module. The following questions and answers do not cover all possible questions, but are representative of the more common ones. Q: What happens when my processor faults? A: All outputs will turn off. In a remote chassis, the status of the outputs when the processor faults is dependent upon the last state bit.
D-2 Frequently Asked Questions Q: Can I connect all of my outputs to the same output device? A: Any or all of the 4 module outputs can go to the same output device, as long as the output commons and Vcc are the same and the total output current is less than 1.5 A. Q: Can I connect all of my inputs to the same input device? A: You can if the device supplies enough current to drive multiple inputs. Q: How does the module make rate calculations? A: See Rate Value on page 2-10.
Appendix E Comparing 1746-HSCE2 to 1746-HSCE 1746-HSCE High Speed Counter 1746-HSCE2 Multi-Channel High Speed Counter 1 2 to 4 16-bit (±32,767) 24-bit (±8,388,607) Operating Class Class 3 only. Class 1 or Class 4. Input Voltage 2.8 to 5.5V dc 4.2 to 30V dc Output Current 0.125 A 1.0 A Input Frequency Response 50K Hz 1M Hz Backplane Response Time 60 ms 0.7 to 1.6 ms Module Compatibility Uses M-files. Not compatible with SLC5/01 and 5/02 or 1747-ASB. Supports handshaking.
E-2 Comparing 1746-HSCE2 to 1746-HSCE Publication 1746-UM002B-EN-P - August 2004
Glossary The following terms and abbreviations are used throughout this manual. For definitions of terms not listed here refer to Allen-Bradley’s Industrial Automation Glossary, Publication AG-7.1. class The class of the module (Class 1 or Class 4) determines: (1) its compatibility with various processors; (2) the number of I/O words; (3) its interrupt ability; and (4) the limits for the count and rate values.
Glossary 2 rate value The counts per second (Hz) value that the module reports to the processor. real outputs The actual physical outputs on the module. static parameter A parameter that must not be altered while the counter is running. underflow (counter) The module’s status when the count value would be less than the minimum value. underflow (rate) The module’s status when the rate value is less than the minimum value.
Index A abbreviations G-1 acknowledge bits 4-2 application errors 5-4 counter overflow 5-4 counter underflow 5-4 initialization errors 5-6 OTE instructions 5-6 programming errors 5-6 rate overflow 5-4 soft preset 5-6 underflow 5-4 C cable length A-1 capture value 2-6, 2-7 CE certified A-1 CE mark 3-1 certification A-1 class 1 1-4 ID code 4-1 valid count range 2-12 class 4 1-4 ID code 4-1 valid count range 2-12 control range rate range 2-14 count range 2-12 range type programming bit 4-21 with linear counte
2 Index E EMC Directive 3-1 encoder wiring 3-8–3-10 errors diagnostic 5-2 programming 5-2 European Union 3-1 F fault LED 5-2 floating point converting from 4-5 converting to 4-4 floating point format reading 4-4 writing 4-4 fuses 2-17 G gate/preset mode programming bit settings 4-13 summary 2-8 gate/preset modes 2-6–2-8 gate and preset limitations 2-8 no preset 2-6 soft preset 2-6 store/continue 2-6 store/hold/resume 2-7 store/preset/hold/resume 2-7 store/preset/start 2-7 grounding 3-5 H hardware featu
Index module setup block 4-6, C-1 debug mode selection bit 4-6 error conditions 5-3 interrupt enable bit 4-7 operating mode programming bits 4-8 program range allocation bit 4-7 range allocation values 4-8 rate value format bit 4-7 transmit bit 4-6 N no preset 2-6 O on-state current derating A-3 operating class 1-4, 4-1 class 1 1-4 class 4 1-4 operating mode counter allocation values 4-8 programming bit settings 4-8 summary 2-8 operating modes 2-1 input assignments 2-1 OTE instructions initialization err
4 Index store/preset/hold/resume 2-7 store/preset/start 2-7 T temperature A-1 terminal wiring 3-7 throughput A-3 timing A-3 transmit bits 4-2 turn-off time A-3 turn-on time A-3 U UL listed A-1 underflow 5-4 counter underflow bit 2-19 linear counter 2-9, 4-16 rate underflow bit 2-19 rate value 4-18 up and down pulses 2-3 Publication 1746-UM002B-EN-P - August 2004 V virtual outputs 2-11 W wiring differential encoder 3-8 encoder wiring 3-8 grounding 3-5 important considerations 3-4 input and output conn
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