Instruction Manual
Table Of Contents
- S-3056-1 Distributed Power System SA3100 Drive Configuration and Programming Instruction Manual
- Important User Information
- Contents
- List of Figures
- List of Tables
- Chapter 1 Introduction
- Chapter 2 Configuring the UDC Module, Regulator Type, and Parameters
- 2.1 Adding a Universal Drive Controller (UDC) Module
- 2.2 Entering the Drive Parameters
- 2.3 Configuring the Vector with Constant Power Regulator
- 2.4 Configuring the Volts per Hertz (V/Hz) Regulator
- 2.5 Configuring Flex I/O
- 2.6 Generating Drive Parameter Files and Printing Drive Parameters
- Chapter 3 Configuring the UDC Module’s Registers
- 3.1 Register and Bit Reference Conventions Used in this Manual
- 3.2 Flex I/O Port Registers (Registers 0-23)
- 3.3 UDC/PMI Communication Status Registers (Registers 80-89/1080-1089)
- 3.4 Command Registers (Registers 100-199/1100-1199)
- 3.5 Feedback Registers (Registers 200-299/1200-1299)
- 3.6 Application Registers (Registers 300-599, Every Scan) (Registers 1300-1599, Every Nth Scan)
- 3.7 UDC Module Test I/O Registers (Registers 1000-1017)
- 3.8 Interrupt Status and Control Registers (Registers 2000-2047)
- Chapter 4 Application Programming for DPS Drive Control
- Chapter 5 On-Line Operation
- Appendix A SA3100 Vector Regulator Register Reference
- Appendix B SA3100 Volts / Hertz Regulator Register Reference
- Appendix C SA3100 Local Tunable Variables
- Appendix D Vector with Constant Power Regulator
- Appendix E Volts per Hertz (V/Hz) Regulator
- Appendix F Status of Data in the AutoMax Rack After a STOP_ALL Command or STOP_ALL Fault
- Appendix G Torque Overload Ratio Parameter Precautions
- Appendix H Default Carrier Frequency and Carrier Frequency Limit for Drive Horsepower Ranges
- Appendix I Vector with Constant Power Parameter Entry Example
- Index
Configuring the UDC Module’s Registers
3-29
Drive Status Register (Continued) 200/1200
Fault Detected Bit 8
The PMI Regulator sets the Fault Detected
status bit if any fault is detected. This bit is
reset by bit 8 of register 100/1100.
Hex Value: 0100H
Sug. Var. Name: FLT@
Access: Read only
UDC Error Code: N/A
LED: N/A
See the description of the Drive Fault register (202/1202) for more information.
Warning Detected Bit 9
The Warning Detected status bit is set if any
warning is detected. This bit is reset by bit 9
of register 100/1100.
Hex Value: 0200H
Sug. Var. Name: WRN@
Access: Read only
UDC Error Code: N/A
LED: N/A
See the description of the Drive Warning register (203/1203) for more information.
CCLK Synchronized Bit 14
The PMI Regulator sets the CCLK
Synchronized status bit when CCLK in the
UDC module is synchronized with CCLK in
the PMI Regulator.
Hex Value: 4000H
Sug. Var. Name: CCLK_OK@
Access: Read only
UDC Error Code: N/A
LED: N/A
This bit is set to zero if CCLK is not turned on in the AutoMax rack or if there have
been two consecutive instances when CCLK is not synchronized after the
application task has turned CCLK on. In this case, the feedback data from the PMI
is not current.
This bit should normally be used only in the start permissive logic for the drive
(which must be true only once to start the drive). It does not normally have to be
used in the run permissive logic for the drive (which must be true during the entire
execution of the task. Note, however, that applications requiring very tight
synchronization between the UDC module and the PMI (e.g., positioning
applications) may require the use of this bit in the run permissive logic.
Refer to the Communication Lost Fault bit description (register 202/1202, bit 15) for
more information.
PMI Operating System Loaded Bit 15
The PMI Regulator sets the PMI Operating
System Loaded status bit when the
operating system has been successfully
downloaded from the UDC module to the
PMI Regulator after power-up.
Hex Value: 8000H
Sug. Var. Name: PMI_OK@
Access: Read only
UDC Error Code: N/A
LED: N/A