Manual

PMI Regulator Motherboard 2-9
Figure 2.4 – PMI Processor Block Diagram
BUS INTERFACE
AND BUFFER
PROM 32 K BY 16 2 WAIT STATES
RAM 128 K BY 16 0 WAIT STATE
32 BIT RISC PROCESSOR
16 Mhz STANDARD
LED
INDICATORS
COMM OK
P. M. F LT EXT. FLT I/O FLT
INTERRUPT CONTROLLER CCLK CNTR SLOTS COMMUNICATIONS
CCLK COUNTER
4 Mhz RATE 1 - 65536 PRELOAD
26-PIN CONN.
PRODUCTION TEST PORT
INTERRUPTS
CLOCK SUBSYSTEM
32 Mhz 16 Mhz 4 Mhz
5V MONITOR
DMA/PROC. I’FACE
COMM.
INTER-
RUPT
D/A CONVERTER
8 BIT BIPOLAR +/-10V @ 10ma SOFTWARE ENABLE
8 -POSITION TERMINAL STRIP
METER 1 METER 2 METER 3 METER 4
METER OUTPUTS
WAIT STATE CONTROLLER BUS FAULT GENERATOR
HIGH SPEED COMMUNICATIONS
10 M-BIT/SEC SDLC-LIKE
PROTOCOL
MANCHESTER
ENCODE/DECODE
DMA CONTROLLER
WATCHDOG TIMER 11.3 MS POWER UP
ENABLE
SAME COMPONENT
BUS REQ.
FIBER-OPTIC TRANSMITTER FIBER-OPTIC RECEIVER
FIBER-OPTIC CONNECTOR
F-0 Tx
F-0 Rx
FLEX I/O INTERFACE AND BUFFER
20-PIN CONNECTOR
FLEX I/O
SYSTEM-WIDE RESET
COMPUTER ADDRESS DATA AND CONTROL BUS
PORT
FIBER-OPTIC CONNECTOR
OK
INTERNAL BACKPLANE INTERFACE