Installation manual

Publication 1747-RM001G-EN-P - November 2008
Data Handling Instructions 5-5
Convert from BCD (FRD)
Use this instruction to convert BCD values to integer values. With Fixed and
SLC 5/01 processors, the source can only be the math register. With SLC 5/02
and higher processors, the source parameter can be a word address in any data
file, or it can be the math register, S:13.
Updates to Arithmetic Status Bits
The arithmetic status bits are found in Word 0, bits 0 to 3 in the status file.
After an instruction is executed, the arithmetic status bits in the status file are
updated.
In the above example, the two rungs cause the processor to verify that the
value at I:0.0 remains the same for two consecutive scans before it executes
the FRD. This prevents the FRD from converting a non–BCD value during an
input value change.
FRD
From BCD
Source N7:58
0156h<
Dest N7:59
0<
FRD
Output Instruction
Fixed SLC
5/01
SLC
5/02
SLC
5/03
SLC
5/04
SLC
5/05
• •••••
Table 5.3 Processor Function
With this Bit The Processor
S:0/0 Carry (C) always resets.
S:0/1 Overflow (V) sets if non-BCD value is contained at the source or the value to
be converted is greater than 32,767; otherwise reset. Overflow
results in a minor error.
S:0/2 Zero (Z) sets if destination value is zero.
S:0/3 Sign (S) always resets.
TIP
We recommend that you always provide ladder logic
filtering of all BCD input devices prior to performing
the FRD instruction. The slightest difference in
point–to–point input filter delay can cause the FRD
instruction to overflow due to the conversion of a
non-BCD digit.
]/[
S:1
15
EQU
EQUAL
Source A N7:1
0
Source B I:0.0
0
MOV
MOVE
Source I:0.0
0
Dest N7:1
0
FRD
FROM BCD
Source I:0.0
0
Dest N7:2
0