Installation manual

Publication 1747-RM001G-EN-P - November 2008
11-10 Understanding Interrupt Routines
Note that STI execution time adds directly to the overall scan time. During the
latency period, the processor is performing operations that cannot be
disturbed by the STI interrupt function.
Latency periods are:
• SLC 5/02 processors interrupts are serviced within 2.4 ms maximum.
• SLC 5/03 and higher processors: If an interrupt occurs while the
processor is performing a multi-word slot update and your interrupt
subroutine accesses that same slot, the multi-word transfer finishes to
completion prior to performing the interrupt subroutine slot access. The
Interrupt Latency Control bit (S:33/8) functions:
• when the bit is set (1), interrupts are serviced within the interrupt
latency time.
• when the bit is clear (0), INTs are serviced per rung, slot, and packet
execution time.
The default state is cleared (0). To determine the interrupt latency with S:33/8
clear, you must calculate the execution time of each and every rung in your
program. Use the longest calculated execution time plus your maximum
interrupt latency.
SLC 5/02 STI SLC 5/03 and Higher
STI with Bit S:33/8 set
SLC 5/03 and Higher
STI with Bit S:33/9
cleared
Input Scan Between slot updates Between word updates Between slot updates
Program Scan Between instruction
updates
Between word updates Between rung updates
Output Scan Between slot updates Between word updates Between slot updates
Communications Between communication
packets
Between word packet
updates
Between
communication packets
Processor Overhead At start and end Between word updates Between word updates
Events in the Processor Operating Cycle