Installation manual

Publication 1747-RM001G-EN-P - November 2008
Understanding Interrupt Routines 11-29
Latency periods are:
• SLC 5/02 interrupts are serviced within 2.4ms maximum.
• SLC 5/03 and higher processors: If an interrupt occurs while the
processor is performing a multi-word slot update and your interrupt
subroutine accesses that same slot, the multi-word transfer finishes to
completion prior to performing the interrupt subroutine slot access. The
Interrupt Latency Control bit (S:33/8) functions:
• when the bit is set (1) interrupts are serviced within the interrupt
latency time.
• when S:33/8 is clear (0), user interrupts occur between rungs and
I/O slot updates.
The default state is cleared (0). To determine the interrupt latency with S:33/8
clear, you must calculate the execution time of each and every rung in your
program.
Interrupt Priorities
Interrupt priorities are as follows.
An executing interrupt can only be interrupted by an interrupt having higher
priority. The I/O interrupt cannot interrupt an executing fault routine, an
executing DII subroutine, an executing STI subroutine, or another executing
I/O interrupt subroutine. If an I/O interrupt occurs while the fault routine,
DII, or STI subroutine is executing, the processor waits until the higher
priority interrupts are scanned to completion. The I/O interrupt subroutine is
then scanned.
Table 11.4 Interrupt Priorities
SLC 5/02 Processor SLC 5/03 and Higher Processors
1. Fault Routine 1. Fault Routine
2. STI Subroutine 2. Discrete Input Interrupt (DII)
3. I/O Interrupt Subroutine (ISR) 3. STI Subroutine
4. I/O Interrupt Subroutine (ISR)