Installation manual

Publication 1747-RM001G-EN-P - November 2008
11-30 Understanding Interrupt Routines
If a major fault occurs while executing the I/O interrupt subroutine, execution
immediately switches to the fault routine. If the fault was recovered by the
fault routine, execution resumes at the point that it left off in the I/O interrupt
subroutine. Otherwise, the fault mode is entered.
If a DII interrupt occurs while executing the I/O interrupt subroutine,
execution immediately switches to the DII subroutine. When the DII
subroutine is scanned to completion, execution resumes at the point that it left
off in the I/O interrupt subroutine.
If the STI timer expires while executing the I/O interrupt subroutine,
execution immediately switches to the STI subroutine. When the STI
subroutine is scanned to completion, execution resumes at the point that it left
off in the I/O interrupt subroutine.
If two or more I/O interrupt requests are detected by the processor at the
same instant, or while waiting for a higher or equal priority interrupt
subroutine to finish, the interrupt subroutine associated with the specialty I/O
module in the lowest slot number is scanned first. For example, if slot 2 (ISR
20) and slot 3 (ISR 11) request interrupt service at the same instant, the
processor first scans ISR 20 to completion, then ISR 11 to completion.
Status File Data Saved
Data in the following words is saved on entry to the I/O interrupt subroutine
and re-written upon exiting the I/O interrupt subroutine.
• S:0 Arithmetic flags
• S:13 and S:14 Math register
• S:24 Index register
I/O Interrupt Parameters
The I/O interrupt parameters below have status file addresses. They are
described here.
TIP
SLC 5/02 specific: It is important to understand that the
I/O pending bit associated with the interrupting slot
remains clear during the time that the processor is waiting
for the fault routine or STI subroutine to finish.
SLC 5/03 and higher processors: The I/O pending bit is
always set when the interrupt occurs. You can examine the
state of these bits within your higher priority interrupt
routines.