Installation manual

Publication 1747-RM001G-EN-P - November 2008
Understanding Interrupt Routines 11-31
• ISR Number - Specifies the subroutine file number that will be executed
when an I/O interrupt is generated by an I/O module. The ISR
Numbers are not part of the status file, but they are part of the I/O
configuration for each slot in the SLC system.
• I/O Slot Enables (Words S:11 and S:12) - These words are bit mapped
to the 30 I/O slots. Bits S:11/1 through S:12/14 refer to slots 1 through
30. Bits S:11/0 and S:12/15 are reserved.
The enable bit associated with an interrupting slot must be set when an
interrupt occurs. Otherwise a major fault will occur. Changes made to
these bits using the Data Monitor function take effect at the next end of
scan.
• I/O Interrupt Pending Bits (Words S:25 and S:26) - These words are bit
mapped to the 30 I/O slots. Bits S:25/1 through S:26/14 refer to slots 1
through 30. Bits S:25/0 and S:26/15 are reserved. The pending bit
associated with an interrupting slot is set when the corresponding I/O
slot interrupt enable bit is clear at the time of an interrupt request. It is
cleared when the corresponding I/O event interrupt enable bit is set, or
when an associated RPI instruction is executed. The pending bit for an
executing I/O interrupt subroutine remains clear when the ISR is
interrupted by a DII, STI, or fault routine.
SLC 5/02 specific: Likewise, the pending bit remains clear if interrupt
service is requested at the time that a higher or equal priority interrupt is
executing (fault routine, STI, or other ISR).
SLC 5/03 and higher processors: This bit is set if interrupt service is
requested at the time a higher or equal priority interrupt is executing
(fault routine, DII, STI, or other ISR).
• I/O Interrupt Enables (Words S:27 and S:28) - These words are bit
mapped to the 30 I/O slots. Bits S:27/1 through S:28/14 refer to slots 1
through 30. Bits S:27/0 and S:28/15 are reserved. The enable bit
associated with an interrupting slot must be set when the interrupt
occurs to allow the corresponding ISR to execute. Otherwise the ISR
will not execute and the associated I/O slot interrupt pending bit will be
set.
SLC 5/02 specific: Changes made to these bits using the data monitor
function or ladder instruction take effect at the next end of scan.
SLC 5/03 and higher processors: Changes made to these bits using the data
monitor function or ladder instruction take effect immediately.