Installation manual
Publication 1747-RM001G-EN-P - November 2008
Understanding Interrupt Routines 11-33
IIE Operation
When true, this instruction sets the I/O interrupt enable bits (S:27/1 through
S:28/14) corresponding to the slots parameter of the instruction. Interrupt
subroutines of the affected slots regain the ability to execute when an interrupt
request is made. If an interrupt was pending (S:25/1 through S:26/14) and the
pending slot corresponds to the IIE slots parameter, the ISR associated with
that slot executes immediately.
IID/IIE Zone Example
In the program below, slots 1, 2, and 7 are capable of generating I/O
interrupts. The IID and IIE instructions in rungs 6 and 12 are included to
avoid having I/O interrupt ISRs execute as a result of interrupt requests from
slots 1, 2, or 7. This allows rungs 7 through 11 to execute without interruption.
IIE IID Example
5
0000
S:1
15
First
Pass
IIE
I/OInterrupt Enable
Slots 1-2,7
IIE
0001
B3:0
0
Any Bit
B3:2
0
Any Bit
0002
B3:0
1
Any Bit
B3:2
0
Any Bit
0003
IID
I/OInterrupt Disable
Slots 1-2,7
IID
0004
B3:0
2
Any Bit
B3:1
2
Any Bit
B3:2
0
Any Bit
0005
B3:0
3
Any Bit
B3:2
0
Any Bit
0006
IIE
I/OInterrupt Enable
Slots 1-2,7
IIE
0007
B3:0
4
Any Bit
B3:2
0
Any Bit
0008
B3:0
5
Any Bit
B3:2
0
Any Bit
0009
END
The following program will demonstrate a IIE and a IID.
The first pass bit S:1/15 and the IIE instruction
in rung 0 are included to insure that the I/O
interrupt function is initialized following a
power cycle. You should include a rung such as
this any time your program contains an IID/IIE
zone or an IID instruction.
The IID instruction in rung 6 clears the I/O
interrupt enable bits associated with slots 1,2,
and 7 (S:27/1, S:27/2, and S:27/7). The IIE
instruction in rung 12 sets these same bits. If an
I/O interrupt is detected by the processor while
the processor is executing rungs 7-11, the
interrupt will be marked as pending. (S:25//1,
S:25/2, and/or S:25/7 will be set.) All interrupts
marked as pending are serviced upon execution
of rung 12. The lowest numbered slot is serviced
first when multiple pending bits are set.
ISR execution
will not occur
between IID
and IIE
instructions.