Installation manual

Publication 1747-RM001G-EN-P - November 2008
SLC Communication Instructions 12-7
Figure 12.2 SLC 5/02 Repeating Messaging Example with MSG Timeout
SLC 5/03 and higher - If a MSG instruction has entered one of the four
channel dependent transmission buffers and is waiting to be transmitted, its
control block will have status bits EN and EW set. If more than four MSG
instructions for that channel are enabled at one time, a channel dependent
overflow queue is used to store the MSG instruction header blocks (not the
data for a MSG write) from the fifth instruction to the fourteenth. If the
channel is configured for Modbus RTU Master, the second through the
eleventh instructions will be added to a channel-dependent overflow queue.
These instructions, queued in a FIFO order, will only have control block status
bit EN set.
If more than 14 (11 for Modbus RTU Master) MSG instructions are enabled at
one time for any one channel, only control block status bit WQ is set, as there
is no room available to currently queue the instruction. This instruction must
be re-scanned with true rung conditions until space exists in the overflow
queue.
0000
EN
DN
ER
MSG
Read/Write Message
Read/Write
Read
Target Device 500CPU
Control Block N9:0
Control Block Length 7
Setup Screen
SLC_502_MSG
0001
N9:0
14
MSG_ST_BIT
EN
DN
TON
Timer On Delay
Timer
T4:0
Time Base 1.0
Preset 5<
Accum 0<
MSG_TIMEOUT
T4:0
DN
MSG_TIMEOUT/DN
L
N9:0
8
MSG_TO_BIT
0002
N9:0
13
MSG_DN_BIT
N9:0
12
MSG_ER_BIT
U
N9:0
15
MSG_EN_BIT
N9:0
8
MSG_TO_BIT
U
N9:0
8
MSG_TO_BIT
0003
END