Installation manual

Publication 1747-RM001G-EN-P - November 2008
SLC Communication Instructions 12-29
• Start Bit ST (bit 14) is set when the processor receives acknowledgment
(ACK) from the target device. The ST bit is reset when the DN, ER, or
TO bit is set. Do not set or reset this bit. It is informational only.
For SLC 5/05 Ethernet (channel 1) communications, the ST bit
indicates internally that the Ethernet daughterboard has received a
command and it is acceptable for a transmission attempt. The command
has not yet been transmitted.
For all broadcast message writes, and for DF1 Radio Modem
communications, the ST bit only indicates that the command has been
successfully transmitted.
• Enable Bit EN (bit 15) is set when rung conditions go true and there is
space available in either the MSG buffer or MSG queue. It remains set
until message transmission is completed and the rung goes false. You
may reset this bit once either the ER or DN bit is set in order to
retrigger a MSG instruction with true rung conditions on the next scan.
Do not set this bit.
• Waiting for Queue Space Bit WQ (Word 7, bit 0)
(1)
is set when the
queue is full. This bit is cleared when space is available in the active
queue. Do not set or reset this bit. It is informational only.
(1)
SLC 5/03 and higher processors only.
TIP
For a MSG write instruction, when the WQ bit is set, or
when only the EN bit is set, your source data is unbuffered.
If your application requires buffered (or snapshot) data, wait
until the EW bit is set before overwriting your source data.
Table 12.10 Setting Bits for Buffered Data
WQ EN EW Description
100MSG not queued or buffered
010MSG is queued, source data not buffered
011MSG and source data is buffered