Installation manual

Publication 1747-RM001G-EN-P - November 2008
2-14 Basic Instructions
Using Status Bits
The accumulated value is retained after the CTU instruction goes false, or
when power is removed from and then restored to the controller. Also, the on
or off status of counter done, overflow, and underflow bits is retentive. The
accumulated value and control bits are reset when the appropriate RES
instruction is enabled. The CU bits are always set prior to entering the REM
Run or REM Test modes.
Count Down (CTD)
The CTD is an instruction that counts false-to-true rung transitions. Rung
transitions can be caused by events occurring in the program such as parts
traveling past a detector or actuating a limit switch.
When rung conditions for a CTD instruction have made a false-to-true
transition, the accumulated value is decremented by one count, provided that
the rung containing the CTD instruction is evaluated between these
transitions.
The accumulated counts are retained when the rung conditions again become
false. The accumulated count is retained until cleared by a reset (RES)
instruction that has the same address as the counter reset.
Table 2.10 Setting CTU Status Bits
This Bit Is Set When And Remains Set Until
One of the Following
Count Up Overflow Bit OV
(Bit 12)
accumulated value wraps
around to -32,768 (from
+32,767) and continues
counting up from there
a RES instruction having the
same address as the CTU
instruction is executed OR
the count is decremented
less than or equal to
+32,767 with a CTD
instruction
Done Bit DN (Bit 13) accumulated value is equal
to or greater than the preset
value
the accumulated value
becomes less than the
preset value
Count Up Enable Bit CU
(Bit 15)
rung conditions are true rung conditions go false OR
a RES instruction having the
same address as the CTU
instruction is enabled
(CD)
(DN)
CTD
COUNT DOWN
Counter C5:1
Preset 120
Accum 0
Output Instruction
Fixed SLC
5/01
SLC
5/02
SLC
5/03
SLC
5/04
SLC
5/05
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