Installation manual

Publication 1747-RM001G-EN-P - November 2008
SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History A-3
OS400, Series A, FRN 1
released: August 1994
Original Release
OS301, Series A, FRN 6
OS400, Series A, FRN 2
released: November 1994
Enhancements
None
OS301, Series A, FRN 7
0S400, Series A, FRN 3
released: March 1995
Enhancements
• Selection of number of data bits and stop bits with generic ASCII
communications added
The Generic ASCII protocol has been expanded to allow 7 or 8 data bits
and 1, 1.5, or 2 stop bits. Generic ASCII communications is selected
when Channel 0 is placed into User Mode.
• Poll Time-out with DF1 Half-duplex Slave Communication
The Poll Time-out feature associated with DF1 Half-duplex Slave
communications on Channel 0 has been changed so that reply data
packets queued to be transmitted when a Poll Time-out occurs will no
longer be purged from the queue. The only event which will now purge
the reply packets is reception of a NAK from the DF1 Master. This
ensures that no matter how much time elapses between when a DF1
Master sends a command packet to the 5/03 and when the master polls
that same 5/03, the reply to that command will be returned by that
5/03. Command data packets generated by MSG Instructions and
which are queued and waiting for transmission will still be purged with
their associated MSG Instruction being errored with the type 0005 code.
• Read of Initialized Data Files during download
The 5/03 processor uses hardware to CRC data files. As a data byte is
written, a CRC is generated in the next byte. When the data is read back
from the processor, the CRC is automatically checked. If it fails, then a
hardware error occurs and the processor resets. Therefore, by the way
the CRC works, data cannot be read from the processor until it has been
written. In one application, the user was continuously polling all of the
processors for information by reading various data files. Since this
polling could happen anytime, they were often colliding with a
download procedure and causing processors to reset. A change was
made in the firmware to not make use of the automatic CRC checking
of data files during a download, thereby preventing this from happening.