Installation manual

Publication 1747-RM001G-EN-P - November 2008
SLC 5/03 (OS30x), SLC 5/04 (OS40x) and SLC 5/05 (OS50x) Firmware History A-9
permissible for the control block to take up User Ladder Program space
as well as use additional user memory for storing runtime ramp
information that is not user accessible.
• File Bit Comparison Instruction (FBC) and Diagnostic Detect
Instruction (DDT)
The FBC and DDT diagnostic instructions are output instructions that
you can use to monitor machine or process operations to detect
malfunctions. If you want to detect malfunction by comparing bits in a
file of real-time inputs with a reference bit file that represents correct
operation, use FBC instruction. If you want to change the reference file
to match the input file, use DDT.
Both the FBC and DDT instructions compare bits in a file of real-time
machine or process values (input file) with bits in a reference file, detect
deviations, and record mismatched bit numbers. They record the
position of each mismatch found and place this information in the result
file. If no mismatches are found, the DN bit is set but the result file
remains unchanged.
The difference between the FBC and DDT instructions is that each time
the DDT instruction finds a mismatch, the processor changes the
reference bit to match the source bit. The FBC instruction does not
change the reference bit. Use the DDT instruction to update your
reference file to reflect changing machine or process conditions.
• Messaging Interrupt Message Reply
Change ‘Message Reply’ disable/enable interrupt scheme to enhance
system performance during STI execution.
• RIO Passthru Function for BSN
The passthru function is now enabled for both the 1747-SN and the
1747-BSN.
• Error Code Trapping ‘Operating System’
The error code trapping is used to get the latest 8 error structures for
hard faults. Error structures are retentive after power cycle, assuming
the battery is connected and charged. Error code trapping only works
for hard faults (0x00—0x0F).
• Updated Operating System Flash programming Algorithm to include
5V ‘JEDEC’
This change is required to allow memory module hardware upgrades to
5V flash technology.