Installation manual

Publication 1747-RM001G-EN-P - November 2008
2-16 Basic Instructions
This instruction provides high-speed counting for fixed I/O controllers with
24 VDC inputs. One HSC instruction is allowed per controller. To use the
instruction, you must cut the jumper as shown below. A shielded cable is
recommended to reduce noise to the input.
High-speed Counter Data Elements
Address C5:0 is the HSC counter 3-word element.
• Word 0 contains the following status bits of the HSC instruction.
– Bit 10 (UA) updates the accumulator word of the HSC to reflect the
immediate state of the HSC when true.
– Bit 12 (OV) indicates if a HSC overflow has occurred.
– Bit 13 (DN) indicates if the HSC preset value has been reached.
– Bit 15 (CU) shows the Enable/Disable state of the HSC instruction.
• Word 1 contains the preset value that is loaded into the HSC when
either the RES instruction is executed, when the Done bit is set, or
when powerup takes place. The valid range is + 1 to + 32767.
• Word 2 contains the HSC accumulator value. This word is updated each
time the HSC instruction is evaluated and when the update accumulator
bit is set using an OTE instruction. This accumulator is read only. Any
value written to the accumulator is overwritten by the actual high-speed
counter on instruction evaluation, reset, or REM Run mode entry.
Table 2.12 High Speed Counter Structure
15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00 Word
CU CD DN OV UN UA Not Used 0
Preset Value 1
Accumulator Value 2
CU Count up enable (Bit 15)
CD Count down enable (Bit 14)
DN Done bit (Bit 13)
OV Overflow bit (Bit 12)
UN Underflow bit (Bit 11)
UA Update accumulator (HSC only) (Bit 10)