Installation manual

Publication 1747-RM001G-EN-P - November 2008
B-14 SLC Status File
S:2/1 Static Config STI (Selectable Timed Interrupt) Enabled Bit
This bit is set in its default condition, or when set by the STE or
STS instruction. If set, it allows execution of the STI if the STI
file (S:31) and STI setpoint (S:30) are non-zero. If clear, when
an interrupt occurs, the STI subroutine does not execute and
the STI Pending bit is set. The STI Timer continues to run when
disabled. The STD instruction clears this bit.
••••
Dynamic
Config
Use the Data Monitor function to set and clear this bit, or
address this bit with your ladder logic program. This bit is set
in its default condition, or when set by the STE or STS
instruction. If set, it allows execution of the STI if the STI file
(word 31) and STI rate (word 30) are non-zero. If clear, the STI
subroutine does not execute and the STI pending bit is set. The
STI timer continues to run. The STD instruction clears this bit.
•••
S:2/2 Status STI (Selectable Timed Interrupt) Executing Bit
When set, this bit indicates that the STI timer has timed out
and the STI subroutine is currently being executed. This bit is
cleared upon completion of the STI routine, powerup, or REM
Run mode entry.
Application example: You can examine this bit in your fault
routine to determine if your STI was executing when the fault
occurred.
••••
S:2/3 Static Config Index Addressing File Range Bit
When clear, the index register can only index within the same
data file of the specified base address. When set, the index
register can index anywhere from data file B3:0 to the end of
the last declared data file. This bit is selected at the time you
save your program.
••••
The SLC 5/03 and higher processors allow you to index from
0:0 to the last data file.
•••
TIP
Change this bit while in the offline mode only. Save the
program after changing the bit.
S:2/4 Static Config Saved with Single Step Test Enabled Bit
When clear, the Single Step Test mode function is not
available. Clear also indicates that debug registers S:16
through S:21 are inoperative. When set, the program can
operate in the Single Step Test mode. See descriptions of S:16
through S:21. When set, your program requires 0.375
instruction words (3 bytes) per rung of additional memory. This
bit is selected at the time you save your program.
•
TIP
This bit is not applicable to the SLC 5/03 and higher processors
since its functionality is always available and requires no
special compile time selection.
•••
Table B.2 Status File Functions (Continued)
Address Classification Description Fixed
5/01
5/02 5/03 5/04 5/05