Installation manual

Publication 1747-RM001G-EN-P - November 2008
SLC Status File B-17
S:2/14 Dynamic
Config
Math Overflow Selection Bit
Set this bit when you intend to use 32-bit addition and
subtraction. When S:2/14 is set, and the result of an ADD,
SUB, MUL, or DIV instruction cannot be represented in the
destination address (underflow or overflow),
• the overflow bit S:0/1 is set,
• the overflow trap bit S:5/0 is set, and
• the destination address contains the unsigned
truncated least significant 16 bits of the result
The default condition of S:2/14 is reset (0). When S:2/14 is
reset, and the result of an ADD, SUB, MUL, or DIV instruction
cannot be represented in the destination address (underflow or
overflow),
• the overflow bit S:0/1 is set,
• the overflow trap bit S:5/0 is set, and
• the destination address contains 32767 if the result
is positive or - 32768 if the result is negative.
••••
TIP
The status of bit S:2/14 has no effect on the DDV instruction.
Also, it has no effect on the math register content when using
MUL and DIV instructions.
To program this feature, use the Data Monitor function to set
or clear this bit. To provide protection from inadvertent data
monitor alteration of your selection, program an unconditional
OTL instruction at address S:2/14 to ensure the new math
overflow operation. Program an unconditional OTU instruction
at address S:2/14 to ensure the original math overflow
operation.
See page 4-7 in this manual for an application example of
32-bit signed math.
Table B.2 Status File Functions (Continued)
Address Classification Description Fixed
5/01
5/02 5/03 5/04 5/05