Installation manual

Publication 1747-RM001G-EN-P - November 2008
SLC Status File B-21
S:4 Status Free Running Clock
Only the first 8 bits (byte value) of this word are assessed by
the processor. This value is zeroed at powerup in the REM Run
mode.
You can use any individual bit of this byte in your user program
as a 50% duty cycle clock bit. Clock rates for S:4/0 to S:4/7
are: 20, 40, 80, 160, 320, 640, 1280, and 2560 ms.
The application using the bit must be evaluated at a rate more
than two times faster than the clock rate of the bit. This is
illustrated in the following example for SLC 5/02 and higher
processors.
•
Dynamic
Config
All 16 bits of this word are assessed by the processor. The
value of this word is zeroed upon power up in the REM Run
mode or entry into the REM Run or REM Test mode. It is
incremented every 10 ms thereafter.
••••
TIP
You can write any value to S:4. It will begin incrementing from
this value.
You can use any individual bit of this word in your user program
as a 50% duty cycle clock bit. Clock rates for S:4/0 to S:4/15
are:
20, 40, 80, 160, 320, 640,1280, 2560, 5120, 10240, 20480,
40960, 81920, 163840, 327680, and 655360 ms
The application using the bit must be evaluated at a rate more
than two times faster than the clock rate of the bit. In the
following example, bit S:4/3 toggles every 80 ms, producing a
160 ms clock rate. To maintain accuracy of this bit in your
application, the instruction using bit S:4/3 (O:1/0 in this case)
must be evaluated at least once every 79.999 ms.
S:5 Minor Error Bits
The bits of this word are set by the processor to indicate that a
minor error has occurred in your ladder program. Minor errors,
bits 0 to 7, revert to major error 0020H if any bit is detected as
being set at the end of the scan. HHT users: If the processor
faults for error code 0020H, you must clear minor error bits
S:5/0-7 along with S:1/13 to attempt error recovery.
•••••
Table B.2 Status File Functions (Continued)
Address Classification Description Fixed
5/01
5/02 5/03 5/04 5/05
( )
] [
S:4
3
O:1
0
160 ms
S:4/3 cycles in 160 ms
Both S:4/3 and Output O:1/0
toggle every 80 ms. O:1/0
must be evaluated at least