Installation manual

Publication 1747-RM001G-EN-P - November 2008
B-24 SLC Status File
S:5/11 Status Battery Low Bit
This bit is set whenever the Battery Low LED is on. The bit is
cleared when the Battery Low LED is off.
••••
S:5/12 Status Discrete Input Interrupt Overflow Bit
This bit is set whenever the DII interrupt occurs while still
executing the DII subroutine or whenever the DII interrupt
occurs while pending or disabled.
•••
S:5/13 Dynamic
Config
Unsuccessful Operating System Load Was Attempted
This bit is set whenever an operating system memory module
load is attempted and is unsuccessful. Unsuccessful loads can
occur when either the protection jumper is in the protect
position or is missing, or if the operating system memory
module is incompatible with the SLC 5/03, SLC 5/04, or SLC
5/05 processors’ hardware platform. Examine the state of this
bit with your user program to diagnose this condition.
•••
S:5/14 Status Channel 0 Modem Lost
This bit indicates the status of the modem connected to
Channel 0 (RS232 serial port). The state of the bit is
determined by:
• the protocol Channel 0 is configured for
• the Control Line selected
• the states of DCD (Data Carrier Detect) and DSR (Data
Set Ready)
If the bit is set, then the modem is not properly connected to
Channel 0 or it is in a state where unreliable communication
exchanges may take place via Channel 0. The following
conditions apply:
• If Channel 0 is disabled or configured for DH-485, the
bit is always cleared.
• If Channel 0 is configured for one of the DF1
protocols in System Mode or Generic ASCII in User
Mode, then the Control Line selection determines
how DCD and DSR affect the modem status:
- If Control Line = NO HANDSHAKING: The bit is
always set.
- If Control Line = FULL-DUPLEX or HALF-DUPLEX
WITHOUT CONTINUOUS CARRIER: The bit is set if DSR
goes inactive and cleared when DSR goes active. (DCD
has no affect on modem status in this case.)
- If Control Line = HALF-DUPLEX WITH CONTINUOUS
CARRIER: The bit is set if either DSR goes inactive or
DCD remains inactive for more than 10 seconds. This
bit is cleared when both DSR and DCD go active.
•••
Table B.2 Status File Functions (Continued)
Address Classification Description Fixed
5/01
5/02 5/03 5/04 5/05