Installation manual

Publication 1747-RM001G-EN-P - November 2008
B-46 SLC Status File
S:32 Status I/O Interrupt Executing
This word indicates the slot number of the specialty I/O
module that generated the currently executing ISR. This
value is cleared upon completion of the ISR, REM Run mode
entry, or upon power-up.
You can interrogate this word inside of your STI subroutine
or fault routine if you wish to know if these higher priority
interrupts have interrupted an executing ISR. You may also
use this value to discern interrupt slot identity when
multiplexing two or more specialty I/O module interrupts to
the same ISR.
I/O interrupts are discussed on page 11-27 of this manual.
••••
You can interrogate this word inside your DII subroutine if
you wish to know if these higher priority interrupts have
interrupted an executing ISR. You may also use this value to
discern interrupt slot identity when multiplexing two or
more specialty I/O module interrupts to the same ISR.
•••
S:33/0 Status Incoming Command Pending (Channel 0)
This bit becomes set when the processor determines that
another node on the channel 0 network has requested
information or supplied a command to it. This bit can be set
at any time. This bit is cleared when the processor services
the request (or command).
Use this bit as a condition of an SVC instruction to enhance
the communication capability of your processor.
•••
S:33/1 Status Message Reply Pending (Channel 0)
This bit becomes set when another node on the channel 0
network has supplied the information that you requested in
the MSG instruction of your processor. This bit is cleared
when the processor stores the information and updates your
MSG instruction.
Use this bit as a condition of an SVC instruction to enhance
the communication capability of your processor.
•••
S:33/2 Status Outgoing Message Command Pending (Channel 0)
This bit is set when one or more channel 0 messages in your
program are enabled and waiting, but no message is being
transmitted at the time. As soon as transmission of a
message begins, the bit is cleared. After transmission, the
bit is set again if there are further messages waiting, or it
remains cleared if there are no further messages waiting.
•••
Table B.4 Status File Functions (Continued)
Address Classification Description Fixed
5/01
5/02 5/03 5/04 5/05