Installation manual

Publication 1747-RM001G-EN-P - November 2008
Data File Organization and Addressing E-21
SLC 5/03 and Higher Processors
The SLC 5/03 and higher processors allow you to monitor the actual state of
each addressed M0/M1 address (or data table). The highlighting appears
normal when compared to the other processor data file. The SLC 5/03’s
performance is degraded to the degree of M0/M1 referenced screen data. For
example, if your screen has only one M0/M1 element, degradation is minimal.
If your screen has 69 M0/M1 elements, degradation is significant.
If you need to show the state of the M0 or M1 addressed bit, you can transfer
the state to an internal processor bit. This is illustrated in the following figure,
where an internal processor bit is used to indicate the true/false state of a rung.
Transferring Data Between Processor Files and M0 or M1 Files
As pointed out earlier, the processor does not contain an image of the M0 or
M1 file. As a result, you must edit and monitor M0 and M1 file data via
instructions in your ladder program. For example, you can copy a block of data
from a processor data file to an M0 or M1 data file or vice versa using the COP
instruction in your ladder program.
The COP instructions below copy data from a processor bit file and integer
file to an M0 file. Suppose the data is configuration information affecting the
operation of the specialty I/O module.
L U
Mf:e.s Mf:e.s Mf:e.s Mf:e.s Mf:e.s
bb bb b
f = file (0 or 1)
When you are monitoring the ladder program in the run or test mode, the programming terminal
does not show these instructions as being true when the processor evaluates them as true.
This rung will not show its true rungstate
because the EQU instruction is always shown
as true and the M0 instruction is always
shown as false.
OTE instruction B3/2 has been added to the
rung. This instruction shows the true or false
s
tate of the rung.