Installation manual

Publication 1747-RM001G-EN-P - November 2008
Math Instructions 4-3
Updates to Arithmetic Status Bits
The arithmetic status bits are found in Word 0, bits 0 to 3 in the controller
status file. After an instruction is executed, the arithmetic status bits in the
status file are updated.
Overflow Trap Bit, S:5/0
Minor error bit (S:5/0) is set upon detection of a mathematical overflow or
division by zero. If this bit is set upon execution of an END statement, a
Temporary End (TND) instruction, or an I/O Refresh (REF), the recoverable
major error code 0020 is declared.
In applications where a math overflow or divide by zero occurs, you can avoid
a CPU fault by using an unlatch (OTU) instruction with address S:5/0 in your
program. The rung must be between the overflow point and the END, TND,
or REF statement.
Updates to the Math Register, S:13 and S:14
Status word S:13 contains the least significant word of the 32-bit value of the
MUL instruction. It contains the remainder for DIV and DDV instructions. It
also contains the first four BCD digits for the Convert from BCD (FRD) and
Convert to BCD (TOD) instructions.
Status word S:14 contains the most significant word of the 32-bit value of the
MUL instruction. It contains the unrounded quotient for DIV and DDV
instructions. It also contains the most significant digit (digit 5) for TOD and
FRD instructions.
Table 4.2 Processor Function
With this Bit The Controller
S:0/0 Carry (C) sets if carry is generated; otherwise cleared.
S:0/1 Overflow (V) indicates that the actual result of a math instruction does
not fit in the designated destination.
S:0/2 Zero (Z) indicates a 0 value after a math, move, or logic instruction.
S:0/3 Sign (S) indicates a negative (less than 0) value after a math, move,
or logic instruction.
TIP
When using floating point, S:13 and S:14 are not used.