User's Manual

ROCKWELL COLLINS
COMPONENT MAINTENANCE MA NUAL with IPL
TDR-94, PART NO 622-9352
(828-8061-003C_8)
TPH6587_08
0.01
10 K
PAL
NC
NC
NC
NC
VSS
VCC
I
I
I
I
I
I
I
I
I
I
I
CLK/I
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
I/0
8351681030
VDD
VDD
VDD
VDD
VDD
VDD
VDD
VDD
GILCRF
VPRBF
VPRCF
DSCIAF
MSLIM
HVPSEN
SYNCLK
SYNDAT
SYNENA
BUSWID
UADD0
CONBLO
CONAHI
TDDILO
TDDIHI
CSDBOD
SBRD3F
URINTO
READYF
HVPRST
WDRSTF
ROMA15
RAMA16
SPARA
SPARB
D1
D2
D4
D5
D7
VSS
VSS
VSS
VSS
ADDR0
ADDR1
ADDR2
ADDR3
ADDR4
ADDR5
ROMENF
RAMEF
DPENAF
NOVRAM
UDPENF
URTENF
D6
ADDR6
ADDR7
ADDR8
ADDR9
ADDR10
ADDR11
ADDR12
ADDR13
ADDR14
ADDR15
AUXD1F
AUXD2F
VPWRDF
VPWREF
MSB1RF
MSB2RF
MSB3RF
GBADRF
INST
RDFIN
WRF
MRSTF
WDOGF
KDOGF
PORT12
PORT14
CSCONT
CSALTA
CSALTB
C1DMLO
C1DMHI
C2DMLO
C2DMHI
C3DMLO
C0DOHI
A1DMLO
A1DMHI
A2DMLO
A2DMHI
TDDOLO
TDDOHI
ATCCLR
ATCIN
ATEIN
HICURR
WRDY
TXR0
TXR1
TXR2
TXR3
VSS
VSS
VSS
VSS
VSS
D3
D0
SPARC
RAMA15
ROMA16
MPRESF
DCRSTF
SBRD2F
SBRD1F
UADD1
UADD2
C3DMHI
C0DOLO
LOCK
ALT1F
MALTF
STINHF
VSS
+5VDC
+5VDC
+5VDC
+5VDC
10 K
+5VDC
DB[0:15]
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
A[0:15]
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
A13
A14
A15
A15
A14
A13
UART
SPARA
1
2
R16
6
J4
21
J25
19
J25
23
J25
16
J25
4
J4
20
J4
15
J4
13
J3
34
J4
26
J4
3
J3
2
J3
12
J3
5
J3
10
J3
9
J3
10
J15
ATCRBS
(6)
9
J15
5
J15
7
J15
18
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
19
20
21
22
24
25
26
27
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
50
51
52
53
54
55
56
57
58
59
62
63
72
71
70
69
68
67
66
65
73
74
75
76
77
78
79
82
83
84
85
86
87
90
89
88
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
114
115
116
117
118
120
119
121
122
125
126
127
128
17
29
49
61
80
92
112
124
16
23
28
48
60
64
81
91
113
123
U19
2
3
4
5
6
7
9
10
11
12
13
16
17
18
19
20
21
23
24
25
26
27
28
14
1
8
22
15
U16
1
2
R14
1
2
C108
WDTRST
WDOG
VPWRE
VPWRD
VPRD
VPRC
SBRD3
SBRD2
RDIN
NOVRAM_ENABLE
MSB3R
MSB2R
MSB1R
MRST
MP_RST
KILL_DOG
GILCR
GBADR
AUXD2
AUXD1
WRL_LOOP
WRDY
URTENF
UADD2
UADD1
UADD0
TYPE_READ_F
TXR3
TXR2
TXR1
TXR0
TDR_MAINT_OUT_LO
TDR_MAINT_OUT_LO
TDR_MAINT_OUT_HI
TDR_MAINT_OUT_HI
TDR_DATA_IN_LO
TDR_DATA_IN_HI
SYNENA
SYNDAT
SYNCLK
ROM_A16_LOOP
ROM_A15_LOOP
RAM_A16
RAM_A15
P1.4_OUT
P1.3_OUT
P1.2_OUT
LOCK_DETECT
HVPSEN
HVPRST
HI_CURRENT
DISCR_IN_A
CSDB_IN
CSDB_CONT_DATA
CSDB_ALT_B_DATA
CSDB_ALT_A_DATA
CONT_IN_LO
CONT_IN_HI
CONT_DATA_3_MUX_LO
CONT_DATA_3_MUX_HI
CONT_DATA_2_MUX_LO
CONT_DATA_2_MUX_HI
CONT_DATA_1_MUX_LO
CONT_DATA_1_MUX_HI
BUSWIDTH
ALTIF
ALE_LOOP
ACH7
A429_ALT2_MUX_LO
A429_ALT2_MUX_HI
A429_ALT1_MUX_LO
A429_ALT1_MUX_HI
(3)
(3)
(3)
(3)
(6)
(6)
(7)
(6)
(2)
(2)
(2)
(2)
(2)
(2)
(9)
(9)
(5)
(5)
(5)
(6)
(1)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(6)
(9)
(9)
(3,9)
(3,9)
(3,9)
(3,9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(9)
(6,9)
(9)
(6)
(6)
(6)
(6)
(6,9)
(6)
(7)
(7)
(1,6,9)
4
J3
6
J3
11
J3
E6
E9
E10
E11
E34
E35
E36
E44
E45
E46
1
TP1
1
TP2
INST _CTL
UART_RST_F
RAM_EN
READY
INST
ROM_LOOP
DP_EN
DISC_RST
CPU-I/O Circuit Card A5A1 (CPN 828-2700-003), Schematic Diagram
Figure 2021 (Sheet 8 of 9)/GRAPHIC 34-50-96-99B-056-A01
34-50-96
Page 2143/2144
May 18/06