Datasheet
10/16
Technical Note
Design procedure Calculation example
4. Selection of diode
When V
IN = 36 V and Io = (max.) 2 A,
When V
IN = 13.2 V, Vo = 5 V, and Io = 1 A,
IRMS=1 X 5 X (13.2-5)/(13.2)
2
=0.485
5. Selection of input capacitor
6. Setting of oscillation frequency
7. Setting of phase compensation (Rc and Cc)
Directions for pattern layout of PCB
* The set values listed above are all reference values. On the actual mounting of the IC, the characteristics may vary with the routing of wirings
and the types of parts in use. In this connection, it is recommended to thoroughly verify these values on the actual system prior to use.
I
RMS=0.485A
Set diode rating with an adequate margin to the maximum load
current. Also, make setting of the rated inverse voltage with
an adequate margin to the maximum input voltage.
A diode with a low forward voltage and short reverse recovery
time will provide high efficiency.
Select a diode of rated current of 2 A or more and rated
withstand voltage of 36 V or more.
Two capacitors, ceramic capacitor C
IN and bypass capacitor C,
should be inserted between the VIN and GND.Be sure to insert
a ceramic capacitor of 1 to 10 µF for the C. The capacitor C
should have a low ESR and a significantly large ripple current.
The ripple current IRMS can be obtained
by the following formula:
Select capacitors that can accept this ripple current.
If the capacitance of CIN and C is not optimum,
the IC may malfunction.
I
RMS=IO X VO X (Vin-VO)/ Vin
2
Referring Fig. 34 and Fig. 35 on the following page, select R
for the oscillation frequency to be used. Furthermore,
in order to eliminate noises, be sure to connect ceramic
capacitors of 0.1 to 1.0 µF in parallel.
The phase margin can be set through inserting a capacitor or
a capacitor and resistor between the INV pin and the FB pin.
Each set value varies with the output coil, capacitance,
I/O voltage, and load. Therefore, set the phase compensation
to the optimum value according to these conditions.
(For details, refer to Application circuit on page 11.)
If this setting is not optimum, output oscillation may result.
Fig.31
1
2
4
3
8
8
6
5
VIN
SW
C
Co
R3
C3
R
T CT
Cin
R1
R2
SIGNAL GND
Cx2
Cx1
L
GND
NMUCP
FB
GND
GND
INV
RT
EN
BD9778HFP
L
O
A
D
2010.02 -
Rev. B
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BD9778F, BD9778HFP, BD9001F, BD9781HFP