Datasheet

15/16
Technical Note
Thermal derating characteristics
Fig.39 Fig.40
10) On the application shown below, if there is a mode in which VIN and each pin potential are inverted, for example,
if the VIN is short-circuited to the Ground with external diode charged, internal circuits may be damaged. To avoid damage,
it is recommended to insert a backflow prevention diode in the series with VIN or a bypass diode between each pin and VIN.
Fig.35
Pin
Backflow prevention diode
Bypass diode
Vcc
8) Ground wiring pattern
It is recommended to separate the large-current GND pattern from the small-signal GND pattern and establish a single
ground at the reference point of the set PCB, so that resistance to the wiring pattern and voltage fluctuations due to
a large current will cause no fluctuations in voltages of the small-signal GND. Prevent fluctuations in the GND wiring pattern
of external parts.
9) Te mperature protection (thermal shut down) circuit
This IC has a built-in temperature protection circuit to prevent the thermal destruction of the IC. As described above,
be sure to use this IC within the power dissipation range. Should a condition exceeding the power dissipation range continue,
the chip temperature Tj will rise to activate the temperature protection circuit, thus turning OFF the output power element.
Then, when the tip temperature Tj falls, the circuit will be automatically reset. Furthermore, if the temperature protection
circuit is activated under the condition exceeding the absolute maximum ratings, do not attempt to use the temperature
protection circuit for set design.
ᰑ Single piece of IC
PCB size: 70 x 70 x 1.6 mm
3
(PCB incorporates thermal via.)
Copper foil area on the front side of PCB: 10.5 x 10.5 mm
2
ᰒ 2-layer PCB (Copper foil area on the reverse side of PCB: 15 x 15 mm
2
)
ᰓ 2-layer PCB (Copper foil area on the reverse side of PCB: 70 x 70 mm
2
)
ᰔ 4-layer PCB (Copper foil area on the reverse side of PCB: 70 x 70 mm
2
)
ᰑ Single piece of IC
ᰒ When mounted on ROHM standard PCB
(Glass epoxy PCB of 70 mm x 70 mm x 1.6 mm)
10
9
8
7
6
5
4
3
2
1
0
ᰔ7.3W
?K@GCLRRCKNCP ?RSP CăR_ĪŊī
ᰓ5.5W
ᰒ2.3W
ᰑ1.4W
25 50 75
HRP7
100 125 150
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
ᰒ
ᰑ
2505075
SOP8
100 125 150
NMUCPBGQQGN?RGML
ă
PD
[
W
]
NMUCPBGQQGN?RGML
ă
PD
[
W
]
?K@GCLRRCKNCP ?RSP CăR_ĪŊī
BD9778F
BD9001F
BD9778F, BD9778HFP, BD9001F, BD9781HFP
2010.02 - Rev. B
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
7) IC pin input (Fig. 37)
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements to keep them isolated.
P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a parasitic diode
or transistor. For example, the relation between each potential is as follows:
When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
When Pin B > GND > Pin A, the P-N junction operates as a parasitic transistor. Parasitic diodes can occur inevitably in the
structure of the IC. The operation of parasitic diodes can result in mutual interference among circuits, operational faults,
or physical damage. Accordingly
, methods by which parasitic diodes operate, such as applying a voltage that is lower than
the GND (P substrate) voltage toan input pin, should not be used.