Datasheet

Technical Note
3/21
BR24T□□□-W Series
www.rohm.com
2011.1 - Rev.H
© 2011 ROHM Co., Ltd. All rights reserved.
Sync data input / output timing
SDA
tSU :ST A tSU :ST OtHD:STA
START BIT
STOP BIT
SCL
Input read at the rise edge of SCL
Data output in sync with the fall of SCL
Fig.1-(a) Sync data input / output timing
Fig.1-(b) Start-stop bit timing
Fig.1-(c) Write cycle timing
Fig.1-(d) WP timing at write execution
Fig.1-(e) WP timing at write cancel
tHIGH:WP
WP
SDA
D1 D0 ACK ACK
DATA(1)
DATA(n)
tWR
SCL
SDA
W rite data
n-th address)
Stop condition Start condition
SCL
WR
ACK
D0
Absolute maximum ratings (Ta=25)
Parameter symbol Limits Unit
Impressed voltage V
CC
-0.3+6.5 V
800 (DIP-T8)
*1
450 (SOP8)
*2
450 (SOP-J8)
*3
300 (SSOP-B8)
*4
330 (TSSOP-B8)
*5
310 (TSSOP-B8J)
*6
310 (MSOP8)
*7
Permissible
dissipation
Pd
300 (VSON008X2030)
*8
mW
Storage
temperature range
Tstg 65+150
Action
temperature range
Topr 40+85
Terminal voltage 0.3Vcc+1.0 V
Memory cell characteristics (Ta=25, Vcc=1.75.5V)
Limits
Parameter
Min. Typ. Max
Unit
Number of data rewrite times
*1
1,000,000
Times
Data hold years
*1
40
Years
*1
Not 100% TESTED
Recommended operating conditions
Parameter Symbol Limits Unit
Power source voltage Vcc
1.75.5
Input voltage V
IN
0Vcc
V
When using at Ta=25 or higher, 8.0mW(*1), 4.5mW(*2,*3),
3.0mW(*4,*8), 3.3mW(*5), 3.1mW(*6, *7) to be reduced per 1.
Electrical characteristics
(
Unless otherwise specified, Ta=40+85
℃、
VCC=1.85.5V
)
Limits
Parameter Symbol
Min. Typ. Max.
Unit Conditions
“H” input voltage 1 V
IH1
0.7Vcc Vcc+1.0 V
“L” input voltage 1 V
IL1
0.3 0.3Vcc V
“L” output voltage 1 V
OL1
0.4 V I
OL
=3.0mA, 2.5VVcc5.5V (SDA)
“L” output voltage 2 V
OL2
0.2 V I
OL
=0.7mA, 1.7VVcc2.5V (SDA)
Input leak current I
LI
1 1 μA V
IN
=0Vcc
Output leak current I
LO
1 1 μA V
OUT
=0Vcc (SDA)
2.0
Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
BR24T01/02/04/08/16/32/64-W
2.5
Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
BR24T128/256-W
I
CC1
4.5
mA
Vcc=5.5V,f
SCL
=400kHz, t
WR
=5ms,
Byte write, Page write
BR24T512/1M-W
0.5
Vcc=5.5V,f
SCL
=400kHz
Random read, current read,
sequential read
BR24T01/02/04/08/16/32/64/128/256-W
Current consumption
at
action
I
CC2
2.0
mA
Vcc=5.5V,f
SCL
=400kHz
Random read, current read,
sequential read
BR24T/512/1M-W
2.0
Vcc=5.5V, SDASCL=Vcc
A0,A1,A2=GND,WP=GND
BR24T01/02/04/08/16/32/64/128/256-W
Standby current I
SB
3.0
μA
Vcc=5.5V, SDASCL=Vcc
A0, A1, A2=GND, WP=GND
BR24T512/1M-W
Radiation resistance design is not made.
*1 BR24T512/1M-W is a
t
ar
g
et value because it is develo
p
in
g
.
Action timing characteristics
(Unless otherwise specified, Ta=40+85, VCC=1.75.5V)
Limit
Parameter Symbol
Min.
Typ. Max.
Unit
SCL frequency fSCL
400
kHz
Data clock “HIGH“ time tHIGH 0.6
μs
Data clock “LOW“ time tLOW 1.2
μs
SDA, SCL rise time
*1
tR
0.3
μs
SDA, SCL fall time
*1
tF
0.3
μs
Start condition hold time tHD:STA 0.6
μs
Start condition setup time tSU:STA 0.6
μs
Input data hold time tHD:DAT 0
ns
Input data setup time tSU:DAT 100
ns
Output data delay time tPD 0.1
0.9
μs
Output data hold time tDH 0.1
μs
Stop condition setup time tSU:STO 0.6
μs
Bus release time before transfer start tBUF 1.2
μs
Internal write cycle time tWR
5
ms
Noise removal valid period (SDA, SCL terminal) tI
0.1
μs
WP hold time tHD:WP 1.0
μs
WP setup time tSU:WP 0.1
μs
WP valid time tHIGH:WP 1.0
μs
*1 Not 100% TESTED.
BR24T512/1M-W is a target value because it is developing.
SCL
SDA
WP
DATA(1)
tSU:WP
DATA(n)
D1
D0 ACK
ACK
tWR
tHD:WP
Stop condition
SDA
(入力)
SDA
(出力)
tHD:STA tHD:DAT
tSU :DAT
tBU F
tPD tDH
tLO W
tHIGHtR tF
SCL
(input)
(output)
*1
*1
*1