User`s manual

RTD Embedded Technologies, Inc. | www.rtd.com 21 FPGA35S6 User’s Manual
4.3.1 BUS CONNECTORS
CN1 (Top) & CN2 (Bottom): PCIe Connector
The PCIe connector is the connection to the system CPU. The position and pin assignments are compliant with the PCI/104-Express
Specification. (See PC/104 Specifications on page 29)
The FPGA35S6 is a “Universal” board, and can connect to either a Type 1 or Type 2 PCIe/104 connector.
4.3.2 JUMPERS
JP1, JP2, JP3, JP4, JP5, & JP6: Pull up/Pull down Jumper
JP1, JP2, JP3, JP4, JP5, and JP6 are 3-pin two position jumpers that are used to set pull up or pull downs options on the I/O signal lines of
CN4 and C5. Refer to Table 11 and Table 12 to determine which I/O pins are effected by each jumper.
Table 13: Pull up/Pull down Jumper options
Setting
Description
1-2
I/O is pulled up to 3.3V or 5V (Set by B1 and B2)
2-3
I/O is pulled down to GND
No Jumper
I/O has no pull up/pull down
JP7: Reserved
JP7 is reserved, and must be left open.
4.3.3 SOLDER JUMPER
B1: Pull up Voltage
Solder jumper B1 are used to set the pull up voltage for JP1, JP2 and JP3.
Table 14: B1 Pull up Voltage
Setting
Description
1-2
Sets Pull up voltage to 3.3V
2-3
Sets Pull up voltage to 5V
B2: Pull up Voltage
Solder jumper B1 are used to set the pull up voltage for JP4, JP5 and JP6.
Table 15: B2 Pull up Voltage
Setting
Description
1-2
Sets Pull up voltage to 3.3V
2-3
Sets Pull up voltage to 5V